Isolation manufacturing method for semiconductor structures

1. A method, comprising:

providing a semiconductor structure that includes a semiconductor substrate and a first semiconductor material extending from a first region to a second region over the semiconductor substrate, wherein the semiconductor substrate and the first semiconductor material have different crystalline orientations in both the first region and the second region;

removing a portion of the first semiconductor material in the second region to form a recess, the recess exposing a sidewall of the first semiconductor material disposed in the first region and a top surface of the semiconductor substrate in the second region;

forming a dielectric material covering the sidewall;

while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and

forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

2. The method of claim 1 , wherein:

the first semiconductor material includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, the first and second semiconductor layers having different material compositions; and

the second semiconductor material includes a plurality of third semiconductor layers interleaved with a plurality of fourth semiconductor layers, the third and fourth semiconductor layers having different material compositions.

3. The method of claim 2 , wherein:

the pluralities of first and third semiconductor layers include the same material composition that contains silicon; and

the pluralities of second and fourth semiconductor layers include silicon germanium having different germanium concentrations.

4. The method of claim 1 , wherein:

the first semiconductor material is in a first crystalline structure with a top surface on a (110) crystal plane; and

the second semiconductor material is in a second crystalline structure with a top surface on a (100) crystal plane.

5. The method of claim 4 , wherein the second semiconductor material further includes a plurality of third semiconductor layers interleaved with a plurality of fourth semiconductor layers, the third semiconductor layers including silicon, the fourth semiconductor layers including silicon germanium.

6. The method of claim 1 , wherein the forming of the dielectric material covering the sidewall includes:

depositing the dielectric material covering the semiconductor structure; and

removing a portion of the dielectric material from a top surface of the semiconductor structure, wherein another portion of the dielectric material covering the sidewall remains.

7. The method of claim 1 , wherein the removing of the portion of the first semiconductor material includes:

forming a hard mask covering the first semiconductor material in the first region; and

etching the first semiconductor material in the second region to form the recess.

8. The method of claim 7 , wherein the hard mask and the dielectric material have different etch selectivity.

9. The method of claim 1 , wherein the dielectric material includes a metal oxide.

10. The method of claim 1 , wherein a bottom surface of the second semiconductor material in the second region is lower than a bottom surface of the first semiconductor material in the first region.

11. A method of forming a semiconductor device, comprising:

providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, the first semiconductor layers having a different material composition than the second semiconductor layers and the first and second semiconductor layers being alternatingly disposed with respect to each other in a vertical direction;

forming a patterned mask over a first region of the substrate;

while the patterned mask is over the first region, removing the pluralities of first and second semiconductor layers in a second region of the substrate such that a sidewall of the pluralities of first and second semiconductor layers in the first region is exposed;

conformally depositing a dielectric material layer over the substrate including the sidewall, wherein the dielectric material layer includes a metal oxide;

while the dielectric material layer is disposed on the sidewall, epitaxially growing a plurality of third semiconductor layers and a plurality of fourth semiconductor layers in the second region, the plurality of third semiconductor layers having a different material composition than the plurality of fourth semiconductor layers and the pluralities of third and fourth semiconductor layers being alternatingly disposed with respect to each other in the vertical direction, wherein a bottommost portion of the pluralities of third and fourth semiconductor layers is lower than a bottommost portion of the pluralities of first and second semiconductor layers; and

patterning the pluralities of first, second, third, and fourth semiconductor layers to form a first fin in the first region and a second fin in the second region.

12. The method of claim 11 , further comprising performing an anisotropic etching to remove a portion of the dielectric material layer from a top surface of the substrate, wherein another portion of the dielectric material layer disposed on the sidewall remains.

13. The method of claim 11 , wherein:

the epitaxially growing of the plurality of third semiconductor layers and the plurality of fourth semiconductor layers includes epitaxially growing silicon germanium.

14. The method of claim 13 , wherein:

the plurality of first semiconductor layers and the plurality of third semiconductor layers include the same material composition that contains Si;

the plurality of second semiconductor layers includes Si 1-x Ge x , wherein x is less than 0.5; and

the plurality of fourth semiconductor layers includes Si 1-y Ge y , wherein y is larger than 0.5.

15. The method of claim 11 , wherein each of the pluralities of first, second, third, and fourth semiconductor layers grows from a crystal plane with the same Miller indices.

16. The method of claim 11 , further comprising:

removing a portion of the plurality of second semiconductor layers in the first fin such that a portion of the plurality of first semiconductor layers is suspended in a first space;

forming a first gate stack over the first fin, wherein a portion of the first gate stack wraps around the portion of the plurality of first semiconductor layers;

removing a portion of the plurality of third semiconductor layers in the second fin such that a portion of the plurality of fourth semiconductor layers is suspended in a second space; and

forming a second gate stack over the second fin, wherein a portion of the second gate stack wraps around the portion of the plurality of fourth semiconductor layers.

17. A semiconductor structure, comprising:

a semiconductor substrate having a first region and a second region;

a first semiconductor structure disposed over the semiconductor substrate within the first region;

an oxide layer stacked between the semiconductor substrate and the first semiconductor structure; and

a second semiconductor structure disposed over the semiconductor substrate within the second region,

wherein in a plane intersecting the first and second semiconductor structures, the first semiconductor structure has a (110) crystal plane and the second semiconductor structure has a (100) crystal plane, the plane being parallel to a top surface of the semiconductor substrate.

18. The semiconductor structure of claim 17 , wherein:

the first semiconductor structure includes a first plurality of nanowires stacked over one another; and

the second semiconductor structure includes a second plurality of nanowires stacked over one another.

19. The semiconductor structure of claim 17 , wherein:

the first semiconductor structure includes a fin structure; and

the second semiconductor structure includes a plurality of nanowires stacked over one another.

20. The semiconductor structure of claim 17 , further comprising:

a silicon oxide layer disposed over the semiconductor substrate within the first region, wherein the silicon oxide layer is directly under the first semiconductor structure.