Semiconductor device structure and method of forming the same
A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.
1. A semiconductor device structure, comprising:
a substrate having a well;
a fin structure extending from the well;
a capping layer surrounding a top surface and side surfaces of the fin structure, wherein a thickness of a top portion of the capping layer above the fin structure is greater than a thickness of a sidewall portion of the capping layer; and
a dielectric oxide layer over the substrate and covering the capping layer, wherein a thickness of a top portion of the dielectric oxide layer above the capping layer is greater than a thickness of a sidewall portion of the dielectric oxide layer.
2. The semiconductor device structure of claim 1 , wherein the fin structure comprises silicon germanium.
3. The semiconductor device structure of claim 1 , wherein the fin structure comprises silicon phosphoric, silicon carbide, or a combination thereof.
4. The semiconductor device structure of claim 1 , wherein the thickness of the top portion of the dielectric oxide layer is greater than the thickness of the sidewall portion of the dielectric oxide layer by 10 angstroms to 50 angstroms.
5. The semiconductor device structure of claim 1 , wherein the dielectric oxide layer comprises silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.
6. The semiconductor device structure of claim 1 , wherein the thickness of the top portion of the capping layer above the fin structure and the thickness of the sidewall portion of the capping layer are at least 3 angstroms.
7. The semiconductor device structure of claim 1 , further comprising:
a liner layer conformal to side surfaces of a protruded portion of the well; and
an isolation feature over the substrate and the liner layer.
8. The semiconductor device structure of claim 1 , further comprising a metallic gate structure over the dielectric oxide layer.
9. A semiconductor device structure, comprising:
a substrate having a first well of a first type and a second well of a second type, wherein the first type is different from the second type;
a first fin structure extending from the first well;
a second fin structure extending from the second well;
a capping layer surrounding a top surface and side surfaces of each of the first fin structure and the second fin structure; and
a dielectric oxide layer over the substrate and covering the capping layer, wherein the dielectric oxide layer has a first top portion over the first fin structure, a second top portion over the second fin structure, and a U-shaped portion connecting the first top portion and the second top portion, and a bottommost part of the U-shaped portion laterally extending along STI region has a thickness smaller than thicknesses of the first and second top portions, and the thickness of the first top portion of the dielectric oxide layer above the capping layer is greater than a thickness of each of sidewall parts of the U-shaped portion of the dielectric oxide layer.
10. The semiconductor device structure of claim 9 , wherein the first fin structure comprises silicon germanium, and wherein the second fin structure comprises silicon phosphoric, silicon carbide, or a combination thereof.
11. The semiconductor device structure of claim 9 , wherein the thickness of the top portion of the dielectric oxide layer is greater than the thickness of each of the sidewall parts of the U-shaped portion of the dielectric oxide layer by 10 angstroms to 50 angstroms.
12. The semiconductor device structure of claim 9 , wherein the dielectric oxide layer comprises silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.
13. The semiconductor device structure of claim 9 , wherein a thickness of a top portion of the capping layer and a thickness of each of sidewall portions of the capping layer are at least 3 angstroms.
14. The semiconductor device structure of claim 9 , further comprising a gate dielectric over the dielectric oxide layer.
15. A semiconductor device structure, comprising:
a substrate having a well;
a fin structure extending from the well;
a capping layer covering the fin structure; and
a dielectric oxide layer having a top portion over a top surface of the fin structure and a sidewall portion over a side surface of the fin structure, wherein a thickness of the top portion of the dielectric oxide layer is greater than a thickness of the sidewall portion of the dielectric oxide layer, wherein the capping layer has a top portion in contact with the top portion of the dielectric oxide layer and a sidewall portion in contact with the sidewall portion of the dielectric oxide layer, and a thickness of the top portion of the capping layer is greater than a thickness of the sidewall portion of the capping layer.
16. The semiconductor device structure of claim 15 , wherein the fin structure comprises silicon germanium.
17. The semiconductor device structure of claim 15 , wherein the fin structure comprises silicon phosphoric, silicon carbide, or a combination thereof.
18. The semiconductor device structure of claim 15 , wherein the thickness of the top portion of the dielectric oxide layer is greater than the thickness of the sidewall portion of the dielectric oxide layer by 10 angstroms to 50 angstroms.
19. The semiconductor device structure of claim 15 , wherein the dielectric oxide layer comprises silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.
20. The semiconductor device structure of claim 15 , further comprising:
a liner layer conformal to side surfaces of a protruded portion of the well; and
an isolation feature over the substrate and the liner layer.