Methods, circuits, devices and systems for comparing signals
Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.
1. A non-volatile memory device comprising:
at least one non-volatile memory (NVM) cell to generate a first electrical signal as a function of a programmed state of the NVM cell;
at least one reference structure to generate a second electrical signal associated with a reference state; and
an NVM cell reading circuit adapted to:
(a) for each of the at least one non-volatile memory and the at least one reference structure, charge to a fixed voltage a compensation capacitor associated with a sense path of the respective signal of the two signals;
(b) trigger a discharge into a respective sense path each of the charged capacitors to a threshold voltage of a transistor in the respective sense path; and
(c) concurrent with the triggering of the discharge, integrating with the discharge current from each capacitor a respective signal sensed on the respective sense path.
2. The device according to claim 1 , wherein said circuit further includes a cross coupled latch to increase a gain between the two signals.
3. The device according to claim 2 , further wherein said circuit is further adapted to latch the respective signals to create a substantially digital output.
4. The device according to claim 2 , wherein the respective signals sensed on the respective sense path develop substantially continuously.
5. The device according to claim 4 , wherein the respective signals sensed develop substantially linearly.
6. The device according to claim 3 , wherein the circuit includes a group of switches switched to a first charging state to enable said charging and switched to a second discharging state to enable said discharging.
7. The device according to claim 6 , wherein said circuit is further adapted to switch the group of switches to increase said gain and switching the group of switches to enable said latching.
8. A non-volatile memory device comprising:
a non-volatile memory (NVM) cell to generate a first signal as a function of a programmed state of the NVM cell;
a reference structure to generate a second signal; and
a reading circuit including a first compensation capacitor coupled to a first transistor in a first sense path for the first signal, and a second compensation capacitor coupled to a second transistor in a second sense path for the second signal,
wherein the reading circuit is adapted to charge the first and second compensation capacitors, and discharge the first compensation capacitor to a threshold voltage of the first transistor, and discharge the second compensation capacitor to a threshold voltage of the second transistor, while concurrently integrating the first and second signals with the discharge currents of the first and second compensation capacitors.
9. The device according to claim 8 , wherein said reading circuit further includes a cross coupled latch to increase a gain between the first and second signals.
10. The device according to claim 9 , further wherein said reading circuit is further adapted to latch the first and second signals to create a substantially digital output.
11. The device according to claim 9 , wherein the first and second signals sensed on the first and second sense paths develop substantially continuously.
12. The device according to claim 11 , wherein the first and second signals sensed on the first and second sense paths develop substantially linearly.
13. A sense amplifier comprising:
a first branch coupled to a non-volatile memory (NVM) cell and configured to receive a first signal that is a function of a programmed state of the NVM cell; and
a second branch coupled to a reference structure and configured to receive a second signal,
wherein each of the first and second branches comprises a compensation capacitor and a switching module, and wherein the switching module is adapted to charge the compensation capacitor, and to discharge the compensation capacitor to a threshold voltage of a transistor in the respective branch while concurrently receiving and integrating a discharge current of the compensation capacitor with one of the respective first or second signals using the transistor.
14. The sense amplifier according to claim 13 , further comprising a cross coupled latch between the first and second branches to increase a gain between the first and second signals.
15. The sense amplifier according to claim 14 , wherein said switching modules of said first and second branches is further adapted to latch the first and second signals to create a substantially digital output.
16. The sense amplifier according to claim 14 , wherein the sense amplifier is adapted to enable the first and second signals received by the first and second branches to develop substantially continuously.
17. The sense amplifier according to claim 16 , wherein the sense amplifier is further adapted to enable the first and second signals received by the first and second branches to develop substantially linearly.