Semiconductor device and method of fabricating the same
A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.
1. A semiconductor device, comprising:
a semiconductor substrate having first and second surfaces facing each other;
an etch stop pattern in a trench formed in the first surface of the semiconductor substrate;
a first insulating layer on the first surface of the semiconductor substrate; and
a through via penetrating the semiconductor substrate and the first insulating layer, the etch stop pattern surrounding a portion of a lateral surface of the through via, wherein
the through via is in a through hole,
the through hole extends into a pattern hole defined by the etch stop pattern,
the etch stop pattern includes at least one edge defined by top and side surfaces thereof,
the at least one edge includes a first edge exposed by the pattern hole and a second edge covered with the semiconductor substrate, and
the first edge has a more rounded profile than a profile of the second edge.
2. The device of claim 1 , wherein
the through via includes first and second portions, the first portion surrounded by the etch stop pattern and the second portion surrounded by the semiconductor substrate,
the second portion of the through via includes a plurality of convex portions, each of the convex portions protruding toward the semiconductor substrate,
the second portion is connected to the first portion, and
the first portion is closer to the first surface of the semiconductor substrate than the second portion.
3. The device of claim 1 , further comprising:
a device isolation pattern in the semiconductor substrate,
wherein a depth of the etch stop pattern is greater than a depth of the device isolation pattern.
4. The device of claim 1 , wherein the etch stop pattern comprises:
a bottom surface coplanar with the first surface of the semiconductor substrate; and
a top surface facing the bottom surface,
wherein a diameter of the pattern hole is smaller at a level of the bottom surface of the etch stop pattern than at a level of the top surface of the etch stop pattern.
5. The device of claim 1 , further comprising:
a liner layer between the through via and the semiconductor substrate and between the through via and the etch stop pattern.
6. The device of claim 1 , wherein the etch stop pattern is configured to penetrate the semiconductor substrate.
7. A semiconductor device, comprising:
a semiconductor layer;
an etch stop pattern penetrating the semiconductor layer;
a through via in a hole defined by the etch stop pattern, the through via having a portion of a lateral surface surrounded by the etch stop pattern; and
a circuit layer on a surface of the semiconductor layer, the circuit layer covering the etch stop pattern, wherein
the etch stop pattern includes at least one edge defined by top and side surfaces thereof,
the edge includes a first edge exposed by the hole and a second edge covered with the semiconductor layer, and
the first edge has a more rounded profile than a profile of the second edge.
8. The device of claim 7 , wherein the through via fills the hole and is in physical contact with the etch stop pattern.
9. The device of claim 7 , wherein the etch stop pattern comprises:
an inner side surface facing the through via; and
an outer side surface facing the semiconductor layer,
wherein the inner side surface has a more rounded profile than a profile of the outer side surface.
10. The device of claim 7 , wherein
the circuit layer includes a via pad therein, and
the through via penetrates at least a portion of the circuit layer and is coupled to the via pad.
11. A semiconductor device, comprising:
an etch stop pattern in a semiconductor substrate; and
a through via penetrating the semiconductor substrate and extending into the etch stop pattern, the through via having the etch stop pattern along sidewalls of a lower portion of the through via, wherein
the etch stop pattern includes at least one edge defined by top and side surfaces thereof,
the edge includes a first edge exposed by a hole in the etch stop pattern and a second edge covered with the semiconductor substrate, and
the first edge has a more rounded profile than a profile of the second edge.
12. The device of claim 11 , wherein
the semiconductor substrate is along sidewalls of an upper portion of the through via,
the upper portion of the through via includes a plurality of convex portions, each of the convex portions protruding toward the semiconductor substrate, and
the upper portion is connected to the lower portion.
13. The device of claim 11 , further comprising:
a device isolation pattern in the semiconductor substrate,
wherein a depth of the etch stop pattern is greater than a depth of the device isolation pattern.
14. The device of claim 11 , further comprising:
a liner layer between the through via and the semiconductor substrate and between the through via and the etch stop pattern.
15. The device of claim 11 , wherein the through via is in physical contact with the etch stop pattern.