Fully digitally controller for cantilever-based instruments
A controller for cantilever-based instruments, including atomic force microscopes, molecular force probe instruments, high-resolution profilometers and chemical or biological sensing probes. The controller samples the output of the photo-detector commonly used to detect cantilever deflection in these instruments with a very fast analog/digital converter (ADC). The resulting digitized representation of the output signal is then processed with field programmable gate arrays and digital signal processors without making use of analog electronics. Analog signal processing is inherently noisy while digital calculations are inherently “perfect” in that they do not add any random noise to the measured signal. Processing by field programmable gate arrays and digital signal processors maximizes the flexibility of the controller because it can be varied through programming means, without modification of the controller hardware.
1. A method, comprising:
receiving a signal from a cantilever of an atomic force microscope into a controller that includes first and second different kinds of programmable logic devices and a cross point switch that adjusts connections to the first and second different kinds of programmable logic devices;
in a first cycle of operation, changing the connections of the crosspoint switch and processing parameters of at least one of the programmable logic devices, to analyze an amplitude of said signal using a first processing mode for said analyzing; and
in a second cycle of operation, changing the connections of the crosspoint switch and changing processing parameters of at least one of the programmable logic devices, to analyze after said first cycle of operation and carried out with the same hardware as in the first cycle of operation, analyzing the amplitude of said signal using a second processing mode for said analyzing, said second processing mode being different than said first processing mode.
2. A method as in claim 1 , wherein said first processing mode is a digital lock-in mode, and said second processing mode is a peak detector mode.
3. The method as in claim 2 , wherein said first and second different kinds of programmable logic devices are respectively an FPGA and a Digital Signal processor, and said first processing and said second processing are carried out by reprogramming said programmable logic.
4. The method as in claim 3 , wherein said first processing and said second processing are carried out by reprogramming the field programmable gate array.