Methods of error-based read disturb mitigation and memory devices utilizing the same
View Patent ↗A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
1. A memory device, comprising:
a main memory comprising a plurality of memory addresses, each memory address corresponding to a single one of a plurality of word lines and being included in a tracked subset of the plurality of memory addresses, each tracked subset including memory addresses corresponding to more than one of the plurality of word lines; and
a controller operably connected to the main memory and configured to:
track, for each tracked subset, a number of read operations,
scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value corresponding to the first tracked subset, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset, and
update the first threshold value by an amount corresponding to the determined error count.
2. The memory device of claim 1 , wherein the tracked subset is one of: a memory block, a memory superblock, or a set of memory blocks comprising a subset of a memory superblock.
3. The memory device of claim 1 , wherein the portion of data corresponding to each word line is a memory page from each word line of the first tracked subset.
4. The memory device of claim 1 , wherein the portion of data corresponding to each word line is an allocation unit from each word line of the first tracked subset.
5. The memory device of claim 1 , wherein the controller is further configured to:
relocate data from the tracked subset if the error count is determined to exceed a second threshold value.
6. The memory device of claim 1 , wherein the controller is configured to update the first threshold value by adjusting a threshold scaling factor corresponding to the first tracked subset based on the determined error count.
7. The memory device of claim 6 , wherein the controller is further configured to:
calculate the first threshold value based on the threshold scaling factor before scanning.
8. The memory device of claim 1 , wherein the first threshold value corresponds at least in part to a number of erase operations performed on the first tracked subset.
9. The memory device of claim 1 , wherein the main memory is a flash memory.
10. A method of managing a memory device having a plurality of memory addresses, each memory address corresponding to a single one of a plurality of word lines and being included in a tracked subset of the plurality of memory addresses, each tracked subset including memory addresses corresponding to more than one of the plurality of word lines, the method comprising:
tracking, for each tracked subset, a number of read operations,
scanning, in response to the number of read operations for a first tracked subset exceeding a first threshold value corresponding to the first tracked subset, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset, and
updating the first threshold value by an amount corresponding to the determined error count.
11. The method of claim 10 , wherein the tracked subset is one of: a memory block, a memory superblock, or a set of memory blocks comprising a subset of a memory superblock.
12. The method of claim 10 , wherein the portion of data corresponding to each word line is a memory page from each word line of the first tracked subset.
13. The method of claim 10 , wherein the portion of data corresponding to each word line is an allocation unit from each word line of the first tracked subset.
14. The method of claim 10 , further comprising:
relocating data from the tracked subset if the error count is determined to exceed a second threshold value.
15. The method of claim 10 , wherein the updating comprises adjusting a threshold scaling factor corresponding to the first tracked subset based on the determined error count.
16. The method of claim 15 , further comprising:
calculating the first threshold value based on the threshold scaling factor before scanning.
17. The method of claim 10 , wherein the main memory is a flash memory.
18. A memory device, comprising:
a main memory comprising a plurality of memory addresses, each memory address corresponding to a single one of a plurality of word lines and being included in a tracked subset of the plurality of memory addresses, each tracked subset including memory addresses corresponding to more than one of the plurality of word lines; and
a controller operably connected to the main memory and configured to:
scan a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset, and
schedule a subsequent scan for the first tracked subset to occur after a number of read operations are performed on the first tracked subset, wherein the number is based on the determined error count.