Semiconductor device having field-effect structures with different gate materials
A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.
1. A semiconductor device, comprising:
a plurality of first field-effect structures each comprising a polysilicon gate arranged on and in contact with a first gate dielectric; and
a plurality of second field-effect structures each comprising a metal gate arranged on and in contact with a second gate dielectric,
wherein the plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device,
wherein the plurality of first field-effect structures and the plurality of second field-effect structures are vertical field-effect structures having a first electrode formed on a first side of a semiconductor substrate and a second electrode formed on a second side of the semiconductor substrate opposite the first side,
wherein the plurality of first field-effect structures and the plurality of second field-effect structures have a same channel type.
2. The semiconductor device of claim 1 , wherein the first gate dielectric is thinner than the second gate dielectric.
3. The semiconductor device of claim 2 , wherein the first gate dielectric has a thickness in a range between 3 nm and 15 nm, and wherein the second gate dielectric has a thickness in a range between 10 nm and 80 nm.
4. The semiconductor device of claim 1 , wherein each first field-effect structure of the plurality of first field-effect structures forms a transistor cell of a power transistor, and wherein each second field-effect structure of the plurality of second field-effect structures forms a MOS-gated diode.
5. The semiconductor device of claim 4 , wherein each first field-effect structure of the plurality of first field-effect structures comprises a first trench in which the polysilicon gate and the first gate dielectric are disposed, a body region of a second conductivity type and a first source region of a first conductivity type opposite the second conductivity type formed in the body region, and wherein each second field-effect structure of the plurality of second field-effect structures comprises a second trench in which the metal gate and the second gate dielectric are disposed and a second source region of the first conductivity type formed in the body region.
6. The semiconductor device of claim 5 , further comprising a plurality of first source contacts each of which provides an ohmic connection between the polysilicon gate and the first source region and the body region of one of the first field-effect structures of the plurality of first field-effect structures, wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the respective second source region and the body region.
7. The semiconductor device of claim 6 , further comprising a source metallization in ohmic contact with the plurality of first source contacts.
8. The semiconductor device of claim 5 , further comprising a plurality of second source contacts each of which is in ohmic contact with the second source region and the body region of one of the second field-effect structures of the plurality of second field-effect structures, wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the plurality of second source contacts.
9. The semiconductor device of claim 5 , wherein each first trench has a first width in a lateral direction, wherein each second trench has a second width in the lateral direction, and wherein the second width is larger than the first width.
10. The semiconductor device of claim 1 , wherein each first field-effect structure of the plurality of first field-effect structures forms a transistor cell of a first power transistor, and wherein each second field-effect structure of the plurality of second field-effect structures forms a transistor cell of a second power transistor.
11. The semiconductor device of claim 10 , wherein the first gate dielectric has the same thickness as the second gate dielectric.
12. The semiconductor device of claim 10 , wherein each first field-effect structure of the plurality of first field-effect structures comprises a first trench in which the polysilicon gate and the first gate dielectric are disposed, a body region of a second conductivity type and a first source region of a first conductivity type opposite the second conductivity type formed in the body region, and wherein each second field-effect structure of the plurality of second field-effect structures comprises a second trench in which the metal gate and the second gate dielectric are disposed and a second source region of the first conductivity type formed in the body region.
13. The semiconductor device of claim 12 , wherein the polysilicon gate of each first field-effect structure of the plurality of first field-effect structures is electrically insulated from the respective first source region and the body region, and wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the respective second source region and the body region.
14. The semiconductor device of claim 12 , wherein each first trench has a first width in a lateral direction, wherein each second trench has a second width in the lateral direction, and wherein the second width is larger than the first width.
15. The semiconductor device of claim 1 , wherein the polysilicon gate and the first gate dielectric of each first field-effect structure of the plurality of first field-effect structures are disposed above a main surface of the semiconductor substrate, and wherein the metal gate and the second gate dielectric of each second field-effect structure of the plurality of second field-effect structures are disposed above the main surface of the semiconductor substrate.
16. The semiconductor device of claim 15 , wherein each first field-effect structure of the plurality of first field-effect structures forms a transistor cell of a power transistor, and wherein each second field-effect structure of the plurality of second field-effect structures forms a MOS-gated diode.
17. The semiconductor device of claim 16 , further comprising a plurality of first gate contacts which electrically connect the polysilicon gate with the first source region of each first field-effect structure of the plurality of first field-effect structures through a first metallization and first source contacts, wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the respective second source region and the body region.
18. The semiconductor device of claim 1 , wherein each first field-effect structure of the plurality of first field-effect structures comprises a first trench in which the polysilicon gate and the first gate dielectric are disposed, a body region of a second conductivity type and a first source region of a first conductivity type opposite the second conductivity type formed in the body region, and wherein each second field-effect structure of the plurality of second field-effect structures comprises a second trench in which the metal gate and the second gate dielectric are disposed and a second source region of the first conductivity type formed in the body region.
19. The semiconductor device of claim 18 , further comprising an ohmic connection between the polysilicon gate and the first source region and the body region of at least one of the first field-effect structures of the plurality of first field-effect structures, wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the respective second source region and the body region.
20. The semiconductor device of claim 18 , wherein the polysilicon gate of each first field-effect structure of the plurality of first field-effect structures is electrically insulated from the respective first source region and the body region, and wherein the metal gate of each second field-effect structure of the plurality of second field-effect structures is electrically insulated from the respective second source region and the body region.