IP Library Granted Patent US 10,032,724
Granted Patent B2
US 10,032,724 · App. 15/634,656 · Granted Jul 24, 2018

Silicon carbide semiconductor base, method of crystal axis alignment in silicon carbide semiconductor base, and method of manufacturing silicon carbide semiconductor device

Inventors: Yasuyuki Kawada (Tsukuba, JP); Takeshi Tawara (Tsukuba, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/544H01L21/02378H01L21/02433H01L21/02529H01L21/049H01L21/0475H01L22/12H01L29/045H01L29/1608H01L29/4236H01L29/66045H01L29/7397H01L29/7813H01L2223/54493
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Quick Facts
Patent No.
US 10,032,724
App. No.
15/634,656
Granted
Jul 24, 2018
Kind
B2
Abstract

On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree is provided. The mark is created on the silicon carbide substrate by forming the first epitaxial layer of the first conductivity type or the second conductivity type on the front surface of the silicon carbide substrate, detecting a stacking fault from the first epitaxial layer, and confirming the crystal axis direction of the silicon carbide substrate from the detected stacking fault.

Claims (34)

1. A silicon carbide semiconductor base comprising

an epitaxial layer formed on a front surface of a silicon carbide substrate, the epitaxial layer containing a silicon carbide, wherein

a mark is provided in the epitaxial layer, the mark indicating one edge of a stacking fault on the epitaxial layer, thereby indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree.

2. The silicon carbide semiconductor base according to claim 1 , wherein

the mark indicates the crystal axis direction of the silicon carbide substrate within a margin of error of 0.5 degrees.

3. The silicon carbide semiconductor base according to claim 1 , wherein

the mark is provided at an end of the silicon carbide substrate.

4. The silicon carbide semiconductor base according to claim 1 , wherein

a poly-type of the silicon carbide substrate is 4H—SiC.

5. A method of crystal axis alignment in a silicon carbide semiconductor base, the method comprising:

forming an epitaxial layer on a front surface of a silicon carbide substrate, the epitaxial layer containing a silicon carbide;

performing a step of detection of a stacking fault from the epitaxial layer;

confirming a crystal axis direction of the silicon carbide substrate from a detected stacking fault; and

creating a mark indicating the confirmed crystal axis direction.

6. The method according to claim 5 , wherein

when no stacking fault is detected in the step of performing detection of a stacking fault, damage is applied to the epitaxial layer and the epitaxial layer is irradiated with ultraviolet rays so that a stacking fault appears.

7. The method according to claim 6 , wherein

a site of the damage is within a predetermined distance from a secondary orientation flat provided at a position orthogonal to the primary orientation flat that indicates the crystal axis direction of the semiconductor substrate.

8. The method according to claim 5 , wherein

the crystal axis direction of the silicon carbide substrate is confirmed using one edge of the stacking fault as a reference.

9. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming a first epitaxial layer on a front surface of a silicon carbide substrate, the first epitaxial layer containing a silicon carbide of a first conductivity type;

forming a second epitaxial layer on a first side of the first epitaxial layer opposite a second side of the first epitaxial layer, the second side facing the silicon carbide substrate, the second epitaxial layer containing a silicon carbide of a second conductivity type;

detecting a stacking fault from the second epitaxial layer;

confirming a crystal axis direction of the silicon carbide substrate from the detected stacking fault;

creating a mark indicating the confirmed crystal axis direction;

selectively forming a first semiconductor region of the first conductivity type, in the second epitaxial layer, the first semiconductor region having an impurity concentration higher than that of the first epitaxial layer;

forming a trench penetrating the first semiconductor region and the second epitaxial layer, and reaching the first epitaxial layer;

forming in the trench, a gate electrode provided via a gate insulating film;

forming a first electrode to contact the first semiconductor region and the second epitaxial layer; and

forming a second electrode on a rear surface of the silicon carbide substrate, wherein

in forming the trench, a sidewall of the trench is formed parallel to the crystal axis direction, based on the mark indicating the crystal axis direction.

10. The method according to claim 9 , wherein the silicon carbide semiconductor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

11. The method according to claim 9 , wherein the silicon carbide semiconductor device is an IGBT (Insulated Gate Bipolar Transistor).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2017
From: KAWADA, YASUYUKI; TAWARA, TAKESHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 042829/0365 →
Priority Claims (1)
JP 2016-170347 · Aug 31, 2016 · national
Continuity (1)
Related Publication 20180061960A1 · Mar 1, 2018