Vertical sense devices in vertical trench MOSFET

1. A semiconductor device comprising:

a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET) comprising:

a plurality of parallel main trenches, wherein said main trenches comprise a first electrode coupled to a gate of said main-MOSFET; and

a plurality of main mesas between said main trenches, wherein said main mesas comprise a main source and a main body of said main-MOSFET; and

a sense-diode comprising:

a plurality of sense-diode trenches, wherein each of said sense-diode trenches comprises a portion of one of said main trenches; and

a plurality of sense-diode mesas between said source-FET trenches, wherein said sense-diode mesas comprise a sense-diode anode that is electrically isolated from said main source of said main-MOSFET.

2. The semiconductor device of claim 1 wherein said main FET trenches comprise a first electrode coupled to said gate of said main-MOSFET and a second electrode electrically isolated from said main gate electrode.

3. The semiconductor device of claim 1 wherein portions of said main MOSFET surrounds said sense-diode on at least three sides.

4. The semiconductor device of claim 1 further comprising a surface isolation region free of surface metallization between said sense-diode and said main MOSFET on said at least three sides.

5. The semiconductor device of claim 4 wherein portions of said surface isolation region are formed between isolation trenches crossing said parallel main trenches.

6. The semiconductor device of claim 1 further comprising:

at least two first isolation trenches crossing said parallel main trenches.

7. The semiconductor device of claim 6 further comprising:

a plurality of second isolation trenches, formed outside of an active area of said sense-diode, wherein each of said second isolation trenches comprises a portion of one of said main trenches.

8. A semiconductor device comprising:

a vertical trench main MOSFET (main-FET) configured to control a drain source current;

a vertical trench sense-diode (sense-diode) configured to produce a signal corresponding to a temperature of said main-FET; and

an isolation trench configured to isolate said main-FET from said sense-diode,

wherein said isolation trench is formed at an angle to, and intersects a plurality of trenches of said main-FET.

9. The semiconductor device of claim 8 wherein vertical trenches of said main-FET comprise at least two vertically aligned electrodes, electrically insulated from one another.

10. The semiconductor device of claim 9 wherein a lower of said electrodes is coupled to a source of said main-FET.

11. The semiconductor device of claim 9 wherein an upper of said electrodes is coupled to a gate of said main-FET.

12. The semiconductor device of claim 9 wherein said angle is greater than 40 degrees.

13. The semiconductor device of claim 9 wherein said angle is substantially 90 degrees.

14. The semiconductor device of claim 9 wherein a cathode of said sense-diode and a drain terminal of said main-FET are electrically coupled.

15. A semiconductor device comprising:

a main-FET comprising a main-FET source region;

a sense-diode configured to produce a signal corresponding to a temperature of said main-FET, said sense-diode comprising:

a plurality of first trenches formed in a first horizontal dimension configured to isolate a sense-diode anode region from said main-FET source region,

wherein each of said trenches comprises multiple alternating layers of conductors and dielectrics in a vertical dimension; and

at least one second trench in a perpendicular horizontal dimension located between said sense-diode anode region and said main-FET source region and configured to isolate said sense-diode anode region from said main-FET source region; and

a buffer region separating said sense-diode anode region and said main-FET source region.

16. The semiconductor device of claim 15 wherein trenches of said main FET comprise a first electrode coupled to a gate electrode of said main-MOSFET and a second electrode electrically isolated from said gate electrode.

17. The semiconductor device of claim 15 further comprising a surface isolation region free of surface metallization between said sense-diode and said main MOSFET on said at least three sides of said sense-diode.

18. The semiconductor device of claim 15 wherein electrodes within trenches of said sense-diode are electrically isolated from electrodes within trenches of said main-FET.

19. The semiconductor device of claim 15 wherein first and second electrodes within trenches of said sense-diode are electrically coupled to the anode terminal of said sense-diode.