Semiconductor device and manufacturing method thereof
A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.
1. A semiconductor device, comprising:
a substrate comprising a first semiconductor fin;
a first dielectric fin disposed over the substrate and in direct contact with a first sidewall of the first semiconductor fin, wherein a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin;
an isolation structure in contact with the first semiconductor fin and the first dielectric fin, wherein a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin; and
a metal gate structure crossing the first dielectric fin.
2. The semiconductor device of claim 1 , wherein the top surface of the first semiconductor fin and the top surface of the first dielectric fin are substantially coplanar.
3. The semiconductor device of claim 1 , wherein:
the first semiconductor fin has a second sidewall connected to the first sidewall; and
the first dielectric fin has a sidewall connected to the second sidewall of the first semiconductor fin, wherein the second sidewall of the first semiconductor fin and the sidewall of the first dielectric fin are substantially coplanar.
4. The semiconductor device of claim 1 , wherein the first semiconductor fin comprises a base portion and a protruding portion protruding upward from the base portion, and the first dielectric fin is over the base portion of the first semiconductor fin.
5. The semiconductor device of claim 4 , wherein a sidewall of the base portion of the first semiconductor fin and a sidewall of the first dielectric fin are substantially coplanar.
6. The semiconductor device of claim 1 , further comprising a second dielectric fin disposed over the substrate and in contact with a second sidewall of the first semiconductor fin opposite to the first sidewall, wherein a width of the second dielectric fin is substantially equal to the width of the first semiconductor fin.
7. The semiconductor device of claim 1 , wherein the first semiconductor fin comprises a base portion and two protruding portions protruding upward from the base portion, and the first dielectric fin is disposed between and in contact with the two protruding portions.
8. The semiconductor device of claim 1 , further comprising a dummy fin disposed over the substrate and adjacent to the first semiconductor fin.
9. The semiconductor device of claim 8 , further comprising an epitaxy structure disposed on the first semiconductor fin and in contact with the dummy fin.
10. The semiconductor device of claim 8 , wherein the dummy fin is engaged in a part of the isolation structure, and a bottom surface of the dummy fin is spaced from the substrate by the isolation structure.
11. A semiconductor device, comprising:
a substrate;
a first fin structure over the substrate, wherein the first fin structure comprises a semiconductor fin and a first dielectric fin connected to the semiconductor fin, the semiconductor fin is in direct contact with the first dielectric fin, and a top surface of the semiconductor fin and a top surface of the first dielectric fin are substantially coplanar;
a second fin structure over the substrate and adjacent to the first fin structure;
an isolation structure immediately adjacent to the semiconductor fin and the first dielectric fin, wherein a height of the isolation structure is lower than a height of the first dielectric fin;
a first epitaxy structure over the second fin structure;
a gate stack disposed over the first fin structure, wherein the gate stack comprises a gate dielectric and a gate metal; and
an etching stop layer extending along a sidewall of the first epitaxy structure and a sidewall of the first dielectric fin, and terminating prior to reaching a gate metal in the gate stack.
12. The semiconductor device of claim 11 , wherein the first fin structure further comprises a second dielectric fin, and the first dielectric fin and the second dielectric fin are disposed on opposite sides of the semiconductor fin.
13. The semiconductor device of claim 11 , wherein an interface between a bottom of the first dielectric fin and the semiconductor fin of the first fin structure is below a top surface of the isolation structure.
14. The semiconductor device of claim 11 , further comprising:
a second fin structure over the substrate;
a dummy fin disposed between the first fin structure and the second fin structure; and
a second epitaxy structure and a third epitaxy structure disposed respectively on the first fin structure and the second fin structure, wherein the second epitaxy structure and the third epitaxy structure are in contact with the dummy fin.
15. The semiconductor device of claim 14 , further comprising a contact disposed over the substrate and in contact with the second epitaxy structure, the third epitaxy structure, and the dummy fin.
16. A method for manufacturing a semiconductor device, comprising:
forming a plurality of semiconductor fins over a substrate;
forming an isolation layer to conformally cover the semiconductor fins;
patterning at least one of the semiconductor fins to form a first recess defined by the patterned semiconductor fin and the isolation layer;
filling a first dielectric material in the first recess;
performing a CMP process to the first dielectric material to form a first dielectric fin in contact with the patterned semiconductor fin and the isolation layer; and
recessing the isolation layer to form an isolation structure adjacent to the patterned semiconductor fin and the first dielectric fin.
17. The method of claim 16 , wherein forming the isolation layer comprises forming a trench in the isolation layer, and the method further comprises forming a dummy fin in the trench of the isolation layer.
18. The method of claim 17 , further comprising forming a plurality of epitaxy structures respectively on the semiconductor fins and the isolation structure, wherein at least parts of the epitaxy structures are in contact with the dummy fin.
19. The method of claim 17 , further comprising:
forming a mask layer over the substrate and in the trench of the isolation layer, wherein the mask layer exposes portions of the semiconductor fins;
removing the exposed portions of the semiconductor fins to form a second recess over the substrate; and
removing the mask layer to expose the trench of the isolation layer.
20. The method of claim 17 , further comprising:
forming at least one gate stack over the patterned semiconductor fin;
removing a portion of the gate stack to form an opening over the dummy fin; and
forming an isolation feature in the opening.