IP Library Granted Patent US 10,431,545
Granted Patent B2
US 10,431,545 · App. 15/637,641 · Granted Oct 1, 2019

Cross-connected multi-chip modules coupled by silicon bent-bridge interconnects and methods of assembling same

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Quick Facts
Patent No.
US 10,431,545
App. No.
15/637,641
Granted
Oct 1, 2019
Kind
B2
Abstract

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

Claims (62)

1. A multi-chip module, comprising:

a central component;

a first component, wherein the first component is coupled to the central component by a first silicon bent-bridge interconnect; and

a subsequent component, wherein the subsequent component is coupled to the central component by a subsequent silicon-bridge interconnect wherein the first silicon bent-bridge interconnect and the subsequent silicon bent-bridge interconnect are torsioned to form an overall helical form factor.

2. The multi-chip module of claim 1 , further including a third silicon bent-bridge interconnect coupled to the first component, and wherein the third silicon bent-bridge interconnect is torsioned to match the overall helical form factor; and

a fourth component coupled to the first component by the third silicon bent-bridge interconnect.

3. The multi-chip module of claim 1 , further including:

a third silicon bent-bridge interconnect coupled to the first con and wherein the third silicon bent-bridge interconnect is torsioned to match the overall helical form factor;

a fourth component coupled to the first component by the third silicon bent-bridge interconnect; and

a fifth component coupled to the fourth silicon bent-bridge interconnect, wherein the fifth component is adjacent the fourth component.

4. A multi-chip module, comprising:

a central component;

a first component, wherein the first component is coupled to the central component by a first silicon bent-bridge interconnect; and

a subsequent component, wherein the subsequent component is coupled to the central component by a subsequent silicon-bridge interconnect, further including:

a heat sink disposed against the central component, wherein the central component is a central processing unit with a backside surface disposed against the heat sink, wherein the first component is a first memory module with a surface thereof disposed against the heat sink, and wherein the subsequent component is a subsequent component is a subsequent memory module with a surface thereof disposed against the heat sink.

5. The multi-chip module of claim 4 , further including:

a fourth component coupled to the central component by a fourth silicon bent-bridge interconnect; and

a fifth silicon-bridge interconnect coupled to the central component.

6. A method of forming a multi-chip module, comprising:

assembling a central component, a first component and a subsequent component on a carrier;

assembling a first silicon-bridge interconnect between the central component and the first component;

assembling a subsequent silicon-bridge interconnect between the central component and the subsequent component; and

deflecting at least one of the silicon bridge interconnects to form a silicon bent-bridge interconnect, further including:

forming a mass on the carrier to encapsulate the central, first and subsequent components and to partially expose the silicon-bridge interconnects but expose silicon of the silicon-bridge interconnects;

removing at least part of the silicon of the silicon-bridge interconnects but to leave etchstop layers on the silicon-bridge interconnects;

removing the mass; and

removing the carrier.

7. A method of forming a multi-chip module, comprising:

assembling a central component, a first component and a subsequent component on a carrier;

assembling a first silicon-bridge interconnect between the central component and the first component;

assembling a subsequent silicon-bridge interconnect between the central component and the subsequent component; and

deflecting at least one of the silicon bridge interconnects to form a silicon bent-bridge interconnect, further including:

urging the central component onto a heat sink to seat the central component;

deflecting the first silicon-bridge interconnect to form a first silicon bent-bridge interconnect while seating the first component on the heat sink; and

deflecting the subsequent silicon-bridge interconnect to form a subsequent silicon bent-bridge interconnect, while seating the subsequent component on the heat sink.

8. A method of forming a multi-chip module, comprising:

assembling a central component, a first component and a subsequent component on a carrier;

assembling a first silicon-bridge interconnect between the central component and the first component;

assembling a subsequent silicon-bridge interconnect between the central component and the subsequent component; and

deflecting at least one of the silicon bridge interconnects to form a silicon bent-bridge interconnect, further including:

forming a mass on the carrier to encapsulate the central, first and subsequent components and to partially expose the silicon-bridge interconnects but expose silicon of the silicon-bridge interconnects;

removing at least part of the silicon of the silicon-bridge interconnects but to leave etchstop layers on the silicon-bridge interconnects;

removing the mass;

removing the carrier;

urging the central component onto a heat sink to seat the central component;

deflecting the first silicon-bridge interconnect to form a first silicon bent-bridge interconnect while seating the first component on the heat sink; and

deflecting the subsequent silicon-bridge interconnect to form a subsequent silicon bent-bridge interconnect, while seating the subsequent component on the heat sink.

9. A method of forming a multi-chip module, comprising:

assembling a central component, a first component and a subsequent component on a carrier;

assembling a first silicon-bridge interconnect between the central component and the first component;

assembling a subsequent silicon-bridge interconnect between the central component and the subsequent component; and

deflecting at least one of the silicon bridge interconnects to form bent-bridge interconnect, wherein deflecting the at least one silicon-bridge interconnect includes deflecting the first and subsequent silicon-bridge interconnects to form a helical form factor.

10. A method of forming a multi-chip module, comprising:

assembling a central component, a first component and a subsequent component on a carrier;

assembling a first silicon-bridge interconnect between the central component and the first component;

assembling a subsequent silicon-bridge interconnect between the central component and the subsequent component; and

deflecting at least one of the silicon bridge interconnects to form a silicon bent-bridge interconnect, further including assembling a fourth component to the first component by coupling a third silicon-bridge interconnect between the first component and the fourth component, wherein deflecting the at least one silicon-bridge interconnect includes deflecting the first, subsequent silicon-bridge and third interconnects to form a helical form factor.

11. A computing system with a multi-chip module, comprising:

a central component, wherein the central component is a semiconductive device;

a first component, wherein the first component is coupled to the central component by a first silicon bent-bridge interconnect;

a subsequent component, wherein the subsequent component is coupled to the central component by a subsequent silicon-bridge interconnect; and

an external shell that encloses the central component, the first component and the subsequent component, wherein the first silicon bent-bridge interconnect and the subsequent silicon bent-bridge interconnect are torsioned to form an overall helical form factor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056337/0609 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE RECEIVING PARTY PREVIOUSLY RECORDED ON REEL 043335 FRAME 0725. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 3, 2019
From: SEIDEMANN, GEORG; WAIDHAS, BERND; WAGNER, THOMAS; WOLTER, ANDREAS; MILLOU, LAURENT
To: INTEL IP CORPORATION
Reel/Frame 049080/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2017
From: SEIDEMANN, GEORG; WAIDHAS, BERND; WAGNER, THOMAS; WOLTER, ANDREAS; MILLOU, LAURENT
To: INTEL CORPORATION
Reel/Frame 043335/0725 →