IP Library › Granted Patent US 10,340,391
Granted Patent B2
US 10,340,391 · App. 15/637,773 · Granted Jul 2, 2019

Semiconductor device and method for fabricating the same

Inventors: Yen-Chen Chen (Tainan, TW); Xiao Wu (Singapore, SG); Hai Tao Liu (Singapore, SG); Ming Hua Du (Singapore, SG); Shouguo Zhang (Singapore, SG); Yao-Hung Liu (Tainan, TW); Chin-Fu Lin (Tainan, TW); Chun-Yuan Wu (Yunlin County, TW)
Assignee: United Microelectronics Corp.
H01L29/7869H01L29/24H01L29/45H01L29/66969
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Quick Facts
Patent No.
US 10,340,391
App. No.
15/637,773
Granted
Jul 2, 2019
Kind
B2
Abstract

A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Claims (15)

1. A method for fabricating a semiconductor device, comprising:

forming an oxide semiconductor layer, over a substrate;

forming a metal nitride layer over the oxide semiconductor layer;

patterning the metal nitride layer to form a source electrode and a drain electrode of a metal nitride; and

forming a metal-nitride oxidation layer on a surface of the source electrode and the drain electrode,

wherein a metal plasma is provided under a power range of 5 kw to 15 kw and flashing of only N 2 by a range of 30 sccm to 50 sccm for forming the metal nitride layer having reduced oxidation, thereby facilitating reduction of thickness of the metal-nitride oxidation layer to be equal to or less than 0.2 of a thickness of the drain electrode or the source electrode.

2. The method of claim 1 , further comprising:

forming a gate electrode over the substrate; and

forming a gate dielectric layer on the gate electrode, wherein the oxide semiconductor layer is disposed on the gate dielectric layer.

3. The method of claim 1 , further comprising forming an oxidation layer at a bottom of the source electrode and the drain electrode in contact with the oxide semiconductor layer, wherein a thickness of the metal-nitride oxidation layer is larger than a thickness of the oxidation layer.

4. The method of claim 1 , wherein a gap between the source electrode and the drain electrode is in a range of 30 nm to 80 nm.

5. The method of claim 1 , wherein the thickness of the metal-nitride oxidation layer is less than 7 nm.

6. The method of claim 1 , wherein the metal plasma is Ta plasma, so to form the metal nitride by TaN.

7. The method of claim 1 , wherein the oxide semiconductor layer comprises InGaZnO (IGZO), In—Zn—O (IZO), In—Ga—O (IGO), Zn—Sn—O (ZTO), In—Sn—Zn—O (ITZO), Hf—In—Zn—O (HIZO), or Al—Zn—Sn—O (AZTO).

8. The method of claim 1 , wherein the step of forming the metal-nitride oxidation layer is a native oxidation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2017
From: CHEN, YEN-CHEN; WU, XIAO; LIU, HAI TAO; DU, MING HUA; ZHANG, SHOUGUO; LIU, YAO-HUNG; LIN, CHIN-FU; WU, CHUN-YUAN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 042868/0409 →
Continuity (1)
Related Publication 20190006519A1 · Jan 3, 2019