IP Library › Granted Patent US 10,503,523
Granted Patent B2
US 10,503,523 · App. 15/638,741 · Granted Dec 10, 2019

Technologies to improve system boot performance and reliability

Inventors: Ravi Poovalur Rangarajan (Hillsboro, OR); Xiang Ma (Portland, OR); Vincent J. Zimmer (Federal Way, WA)
Assignee: Intel Corporation
G06F9/44505G06F9/24G06F9/4411G06F9/44578
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Quick Facts
Patent No.
US 10,503,523
App. No.
15/638,741
Granted
Dec 10, 2019
Kind
B2
Abstract

Technologies for optimization of a memory controller include a computing device having a memory manager, a memory trainer, and a platform firmware. The memory manager reserves a space in memory of the computing device that is inaccessible to an operating system of the computing device. The memory trainer utilizes the reserved space to perform a memory training to determine configuration settings of the memory controller. After the configuration settings of the memory controller have been determined, the platform firmware configures the memory controller with the determined configuration settings.

Claims (41)

1. A computing device for configuring a memory controller, the computing device comprising:

a processor; and

a memory storing a plurality of instructions, which, when executed by the processor, causes the computing device to:

reserve a space in the memory of the computing device to perform a memory training, wherein the reserved space in the memory is inaccessible to an operating system of the computing device;

perform the memory training within the reserved space to determine configuration settings of the memory controller, wherein to perform the memory training comprises to perform the memory training during normal operation of the computing device, and wherein to perform the memory training during normal operation of the computing device comprises to (i) execute the operating system with the computing device and (ii) perform the memory training contemporaneously with execution of the operating system;

limit access by the operating system to the memory of the computing device in response to the performance of the memory training during normal operation of the computing device; and

configure the memory controller with the determined configuration settings in response to limiting the access to the memory of the computing device.

2. The computing device of claim 1 , wherein to determine the configuration settings comprises to determine a voltage parameter or a timing parameter.

3. The computing device of claim 1 , wherein the plurality of instructions further causes the computing device to store the configuration settings of the memory controller in a data storage of the computing device.

4. The computing device of claim 1 , wherein the plurality of instructions further causes the computing device to:

boot the computing device; and

determine whether there are configuration settings stored in a data storage of the computing device in response to the boot of the computing device;

wherein to configure the memory controller comprises to configure the memory controller with the configuration settings stored in the data storage in response to a determination that there are configuration settings stored in the data storage.

5. The computing device of claim 1 , wherein the plurality of instructions further causes the computing device to resume access by the operating system to the memory of the computing device in response to the configuration of the memory controller with the determined configuration settings.

6. The computing device of claim 1 , wherein the reserved space it the memory comprises a memory bank of the memory to perform the memory training.

7. The computing device of claim 1 , wherein the reserved space in the memory is accessed by a plurality of signal lines of the computing device, wherein the signal lines couple the memory controller to the memory.

8. The computing device of claim 7 , wherein the memory controller and the memory are coupled by a plurality of data signal lines and a plurality of I/O address lines, wherein the signal lines comprise the data signal lines and the I/O address lines.

9. A method for configuring a memory controller, the method comprising:

reserving, by a computing device, a space in a memory of the computing device for performing a memory training, wherein the reserved space in the memory is inaccessible to an operating system of the computing device;

performing, by the computing device, the memory training within the reserved space in the memory of the computing device to determine configuration settings of the memory controller, wherein performing the memory training comprises performing the memory training during normal operation of the computing device, and wherein performing the memory training during normal operation of the computing device comprises (i) executing the operating system with the computing device and (ii) performing the memory training contemporaneously with executing the operating system;

limiting, by the computing device, access by the operating system to the memory of the computing device in response to performing the memory training during normal operation of the computing device; and

configuring, by the computing device, the memory controller with the determined configuration settings in response to limiting the access to the memory of the computing device.

10. The method of claim 9 , further comprising storing, by the computing device, the configuration settings of the memory controller in a data storage of the computing device.

11. The method of claim 9 , further comprising:

booting the computing device; and

determining, by the computing device, whether there are configuration settings stored in a data storage of the computing device in response to booting the computing device;

wherein configuring the memory controller comprises configuring the memory controller with the configuration settings stored in the data storage in response to determining that there are configuration settings stored in the data storage.

12. The method of claim 9 , wherein the reserved space in the memory comprises a memory bank of the memory for performing the memory training.

13. The method of claim 9 , wherein the reserved space in the memory is accessed by a plurality of signal lines of the computing device, wherein the signal lines couple the memory controller to the memory.

14. One or more non-transitory, computer readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

reserve a space in a memory of the computing device for performing a memory training, wherein the reserved space in the memory is inaccessible to an operating system of the computing device;

perform the memory training within the reserved space in the memory of the computing device to determine configuration settings of the memory controller, wherein to perform the memory training comprises to perform the memory training during normal operation of the computing device, and wherein to perform the memory training during normal operation of the computing device comprises to (i) execute the operating system with the computing device and (ii) perform the memory training contemporaneously with executing the operating system;

limit access by the operating system to the memory of the computing device in response to performing the memory training during normal operation of the computing device; and

configure the memory controller with the determined configuration settings in response to limiting the access to the memory of the computing device.

15. The one or more computer readable storage media of claim 14 , further comprising a plurality of instructions that in response to being executed cause the computing device to store the configuration settings of the memory controller in a data storage of the computing device.

16. The one or more computer readable storage media of claim 14 , further comprising a plurality of instructions that in response to being executed cause the computing device to:

boot the computing device; and

determine whether there are configuration settings stored in a data storage of the computing device in response to booting the computing device;

wherein to configure the memory controller comprises to configure the memory controller with the configuration settings stored in the data storage in response to determining that there are configuration settings stored in the data storage.

17. The one or more computer readable storage media of claim 14 , wherein the reserved space in the memory comprises a memory bank of the memory for performing the memory training.

18. The one or more computer readable storage media of claim 14 , wherein the reserved space in the memory is accessed by a plurality of signal lines of the computing device, wherein the signal lines couple the memory controller to the memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2017
From: RANGARAJAN, RAVI POOVALUR; MA, XIANG; ZIMMER, VINCENT J.
To: INTEL CORPORATION
Reel/Frame 043040/0262 →
Continuity (1)
Related Publication 20190004825A1 · Jan 3, 2019