Semiconductor device and method
A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
1. A method comprising:
forming a conductive post on a die;
coupling a test probe to the conductive post with solder; and
etching the solder and the conductive post with a first etching process, the first etching process comprising etching the solder and the conductive post with a same nitric-based etchant such that the conductive post forms no salt or less salt than the solder.
2. The method of claim 1 , wherein the solder contacts a top surface and sidewalls of the conductive post before the etching.
3. The method of claim 2 , wherein etching the solder and the conductive post removes the solder from the top surface and the sidewalls of the conductive post.
4. The method of claim 1 , further comprising:
testing the die after coupling the test probe to the conductive post.
5. The method of claim 4 , wherein the etching is performed after the testing.
6. The method of claim 1 , further comprising:
after etching the solder and the conductive post, forming a dielectric over the die, the dielectric contacting sidewalls of the conductive post.
7. The method of claim 6 , further comprising:
placing the die on a carrier substrate;
forming a via on the carrier substrate adjacent the die; and
encapsulating the die and the via with a molding compound.
8. The method of claim 7 , further comprising:
forming redistribution layers over the die and the via; and
forming external contacts on the redistribution layers.
9. The method of claim 1 , wherein the solder and the conductive post are formed of different materials.
10. A method comprising:
coupling a test probe to a conductive post with a solder;
after coupling the test probe, removing the test probe from the conductive post;
after removing the test probe, removing remaining portions of the solder from the conductive post with an etching process, the etching process including etching the solder with a nitric-based etchant comprising an ion of a transitional metal, and the etching the solder comprising etching the solder from sidewalls and a top surface of the conductive post; and
after removing the remaining portions of the solder from the conductive post, forming a dielectric material on the etched sidewalls and top surface of the conductive post.
11. The method of claim 10 , wherein etching the solder with the nitric-based etchant cleans the conductive post.
12. The method of claim 10 , wherein the conductive post is a copper pillar.
13. The method of claim 10 , the etching process including etching the solder with the nitric-based etchant comprising the ion of a transitional metal such that the conductive post forms no salt or less salt than the solder.
14. A method comprising:
forming a copper pillar on a die;
forming a solder ball on the copper pillar;
reflowing the solder ball to form a solder connection, the solder connection contacting sidewalls of the copper pillar and coupling a test probe to a top surface of the copper pillar;
testing the die with the test probe; and
etching the top surface and the side ails of the copper pillar with a nitric-base etchant to remove the solder ball contacting the sidewalls of the copper pillar.
15. The method of claim 14 , wherein etching the top surface and the sidewalls of the copper pillar comprises performing a plurality of etching steps on the copper pillar with a plurality of etchants, at least one of the plurality of etchants being a nitric-based etchant.
16. The method of claim 14 , further comprising:
forming a dielectric material on the etched sidewalls and the top surface of the copper pillar.
17. The method of claim 16 , further comprising:
planarizing the dielectric material until the top surface of the copper pillar is level with a top surface of the dielectric material.
18. The method of claim 14 , wherein etching the top surface and the sidewalls of the copper pillar removes the solder connection and decouples the test probe from the copper pillar.
19. The method of claim 14 , further comprising:
placing the die on a carrier substrate;
forming a via adjacent the die; and
encapsulating the die and the via on the carrier substrate.
20. The method of claim 19 , further comprising:
forming redistribution layers over the die and the via; and
forming external contacts on the redistribution layers.
21. The method of claim 14 , further comprising:
after the etching, forming a dielectric material on the etched sidewalls and the top surface of the copper pillar, wherein at least a portion of a bottom surface of the dielectric material is below the top surface of the copper pillar.