IP Library Granted Patent US 10,062,604
Granted Patent B2
US 10,062,604 · App. 15/643,488 · Granted Aug 28, 2018

Semiconductor device and method for fabricating the same

Inventors: Ching-Yu Chang (Taipei, TW); Ssu-I Fu (Kaohsiung, TW); Yu-Hsiang Hung (Tainan, TW); Chih-Kai Hsu (Tainan, TW); Wei-Chi Cheng (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/7682H01L21/0228H01L21/02164H01L21/02274H01L21/2815H01L21/28132H01L21/28141H01L21/28247H01L21/31105H01L21/823431H01L21/823456H01L21/823462H01L21/823468H01L21/823864H01L27/0886H01L29/42364H01L29/6653H01L29/6656H01L29/66689H01L29/66719H01L23/485
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Quick Facts
Patent No.
US 10,062,604
App. No.
15/643,488
Granted
Aug 28, 2018
Kind
B2
Abstract

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate and an interlayer dielectric (ILD) layer around the gate structure; and

a spacer enclosing an air gap adjacent to the gate structure and extending to and contacting a top surface of the gate structure, wherein the spacer is composed of a single material and a top surface of the spacer directly on top of the gate structure is lower than a top surface of the ILD layer.

2. The semiconductor device of claim 1 , wherein the gate structure comprises a high-k dielectric layer, a work function metal layer, and a low resistance metal layer.

3. The semiconductor device of claim 2 , wherein the high-k dielectric layer is U-shaped.

4. The semiconductor device of claim 1 , wherein a top surface of the spacer comprises a planar surface.

5. The semiconductor device of claim 1 , further comprising a hard mask on the spacer, wherein a top surface of the hard mask and a top surface of the ILD layer are coplanar.

6. The semiconductor device of claim 5 , wherein the hard mask comprises silicon nitride.

7. The semiconductor device of claim 1 , wherein the spacer comprises silicon dioxide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2017
From: CHANG, CHING-YU; FU, SSU-I; HUNG, YU-HSIANG; HSU, CHIH-KAI; CHENG, WEI-CHI; JENQ, JYH-SHYANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 042927/0727 →
Priority Claims (1)
CN 2016 1 0292063 · May 5, 2016 · national
Continuity (2)
Division 15172161 · Jun 3, 2016
Related Publication 20170323824A1 · Nov 9, 2017