Microfabricated ultrasonic transducers and related apparatus and methods
Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.
1. A method, comprising:
forming a layer of oxide on a first side of a first wafer, the first wafer having a second side opposite the first side;
forming a plurality of cavities in the layer of oxide;
bonding a second wafer with the first wafer such that the second wafer seals the plurality of cavities in the layer of oxide; annealing the first wafer and the second wafer after bonding them together;
thinning the first wafer or the second wafer after the annealing to create a thinned wafer;
etching a plurality of trenches in the thinned wafer, the plurality of trenches defining a plurality of electrode regions of the thinned wafer;
filling the plurality of trenches with an insulating material;
forming metal contacts on the thinned wafer, at least some of the metal contacts corresponding to the plurality of electrode regions;
bonding the thinned wafer with a wafer having integrated circuitry formed therein using the metal contacts on the thinned wafer to contact bonding points on the wafer; and
thinning, after bonding the thinned wafer with the wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer.
2. The method of claim 1 , wherein forming the plurality of cavities in the layer of oxide comprises etching completely through the layer of oxide.
3. A method for fabricating micromachined ultrasound transducers, comprising:
forming a plurality of cavities in a layer of oxide on a first side of a first wafer, the first wafer having a second side opposite the first side;
bonding a second wafer with the first wafer such that the second wafer seals the plurality of cavities in the layer of oxide;
annealing the first wafer and the second wafer after bonding them together the annealing utilizing a first temperature;
thinning the first wafer or the second wafer after the annealing to create a thinned wafer;
etching a plurality of trenches in the thinned wafer, the plurality of trenches defining a plurality of electrode regions of the thinned wafer;
filling the plurality of trenches in the thinned wafer with an insulating material;
forming metal contacts on the plurality of electrode regions of the thinned wafer;
aligning the thinned wafer with an integrated circuit wafer having integrated circuitry formed therein;
bonding the thinned wafer with the integrated circuit wafer having integrated circuitry formed therein using the metal contacts on the thinned wafer to contact bonding points on the integrated circuit wafer, wherein bonding the thinned wafer with the integrated circuit wafer is performed at a second temperature less than the first temperature; and
forming a flexible membrane by thinning, after bonding the thinned wafer with the integrated circuit wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer.