Operating different processor cache levels
A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.
1. A computer program product to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution, the cache hierarchy comprising at least a lower hierarchy level entity and a higher hierarchy level entity, the computer program product comprising:
a computer readable storage medium having computer usable code embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the computer usable program code comprising:
computer usable code configured for sending a fetch request to the cache hierarchy;
computer usable code configured for detecting a miss event from a lower hierarchy level entity;
computer usable code configured for sending a fetch request to a higher hierarchy level entity;
computer usable code configured for scheduling at least one write pass; and
computer usable code configured for writing, in the case of a write pass, data into a directory structure to the respective level cache instead of writing the data to a fetch address register.
2. The computer program product of claim 1 , further comprising scheduling a first write pass and writing directory structures of a lower level hierarchy entity and a higher level hierarchy entity to be invalid.
3. The computer program product of claim 1 , wherein the lower level hierarchy entity is a first level cache of the processor, the higher level hierarchy entity is a second level cache of the processor, and a next higher level hierarchy entity is a third level cache and/or a main memory associated with the processor.
4. The computer program product of claim 1 , further comprising determining, based upon a response from the higher level hierarchy entity, as to whether a hit has been encountered.