SYSTEMS AND METHODS FOR CMOS-INTEGRATED JUNCTION FIELD EFFECT TRANSISTORS FOR DENSE AND LOW-NOISE BIOELECTRONIC PLATFORMS
A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a substrate layer of one dopant type with a gate layer of that dopant type disposed on the substrate, a depletion channel of a second dopant type disposed on the first gate layer, and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor. The second gate layer can separate the depletion channel from the surface, and the depletion channel separates the first gate layer from the second gate layer.
1 . An integrated junction field effect transistor formed as a complementary metal oxide semiconductor, comprising:
a substrate layer of a first dopant type;
an isolation well of a second dopant type disposed above the substrate;
a first gate layer of the first dopant type disposed above the isolation well;
a depletion channel of the second dopant type disposed above the first gate layer; and
a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer.
2 . The transistor as claimed in claim 1 , wherein the isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.
3 . The transistor as claimed in claim 1 , further comprising a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel.
4 . The transistor as claimed in claim 3 , wherein the transistor is free of shallow trench isolation between the second gate layer and each of the source and drain contacts.
5 . The transistor as claimed in claim 3 , further including shallow trench isolation between the second gate layer and each of the source and drain contacts.
6 . The transistor as claimed in claim 1 , wherein the first dopant type is P-type and the second dopant type is N-type.
7 . The transistor as claimed in claim 1 , wherein the first dopant type is N-type and the second open type is P-type.
8 . A plurality of transistors as claimed in claim 1 , configured as an array.
9 . A method of making a junction field effect transistor using a complementary metal oxide semiconductor (CMOS) process, comprising:
providing a substrate layer of a first dopant type;
forming an isolation well of the second dopant type above the substrate;
forming a first gate layer of the first dopant type above the isolation well;
forming a depletion channel of the second dopant type above the first gate layer; and
forming a second gate layer of the first dopant type above the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer.
10 . A method of making the transistor as claimed in claim 9 , wherein the isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.
11 . A method of making the transistor as claimed in claim 9 , further comprising a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel.
12 . A method of making the transistor as claimed in claim 9 , wherein the transistor is free of shallow trench isolation between the second gate layer and each of the source and drain contacts.
13 . A method of making the transistor as claimed in claim 9 , wherein the transistor is formed using a 180 nm process.
14 . A method of making the transistor as claimed in claim 9 , wherein the first dopant type is P-type and the second dopant type is N-type.
15 . A method of making the transistor as claimed in claim 9 , wherein the first dopant type is N-type and the second open type is P-type.
16 . A method of making the plurality of transistors as claimed in claim 9 , configured as an array.