Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
View Patent ↗Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
1. A device comprising:
a first conductive region;
a string of memory cells;
a transistor coupled between the first conductive region and the string of memory cell;
a second conductive region; and
a bipolar junction transistor including a collector and an emitter coupled in series with the second conductive region and the string of memory cells;
a first additional conductive region coupled to the first conductive region;
an additional string of memory cells;
an additional transistor coupled between the first additional conductive region and the additional string of memory cell;
a second additional conductive region; and
an additional bipolar junction transistor including a collector and an emitter coupled in series with the second additional conductive region and the additional string of memory cells, wherein the first bipolar junction transistor includes a base directly coupled to a base of the additional bipolar junction transistor.
2. The device of claim 1 , wherein the first conductive region is part of a data line of the device.
3. The device of claim 2 , wherein the second conductive region is part of a source of the device.
4. The device of claim 1 , wherein the bipolar junction transistor includes an NPN bipolar junction transistor.
5. The device of claim 1 , wherein the bipolar junction transistor includes a PNP bipolar junction transistor.
6. The device of claim 1 , wherein the transistor includes a field effect transistor.
7. The device of claim 1 , wherein the second conductive region and the second additional conductive region are parts of a source of the device.
8. The device of 1 , further comprising:
a third additional conductive region, the third additional conductive region being part of a first data line, and the first conductive region being part of a second data line;
a second additional string of memory cells;
a second additional transistor coupled between the third additional conductive region and the second additional string of memory cell;
a fourth additional conductive region; and
a second additional bipolar junction transistor coupled between the fourth additional conductive region and the additional string of memory cells.
9. The device of claim 8 , wherein the transistor includes a gate coupled to a gate of the second additional transistor.
10. The device of claim 9 , wherein the second conductive region and the fourth additional conductive region are parts of a source of the device.