Semiconductor device
View Patent ↗To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal outputs “false” when “false” is input to the first terminal and the second terminal. The third terminal outputs “true” when “true” is input to the first terminal and the second terminal. The third terminal outputs a truth value that is the same as the previous output, when “true” is input to one of the first terminal and the second terminal and “false” is input to the other of the first terminal and the second terminal. The memory circuit is capable of storing data stored in the latch circuit, while supply of a power supply voltage is stopped. The memory circuit includes a transistor that contains a metal oxide in a channel formation region.
1. A semiconductor device comprising:
a first terminal, a second terminal, a third terminal, a latch circuit, and a memory circuit,
wherein:
the memory circuit comprises first and second memory elements,
each of the first and second memory elements comprises a first transistor containing an oxide semiconductor in a channel thereof, a second transistor, and a capacitor,
in each of the first and second memory elements,
one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, and
the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the latch circuit,
gates of the first transistors in the first and second memory elements are electrically connected to each other,
the third terminal outputs “false” when “false” is input to the first terminal and the second terminal,
the third terminal outputs “true” when “true” is input to the first terminal and the second terminal,
the third terminal outputs a truth value that is the same as a previous output, when “true” is input to one of the first terminal and the second terminal and “false” is input to the other of the first terminal and the second terminal, and
the memory circuit is configured to store data stored in the latch circuit, while supply of a power supply voltage is stopped.
2. The semiconductor device according to claim 1 , wherein the memory circuit comprises a transistor comprising a metal oxide in a channel formation region.
3. A buffer circuit comprising the semiconductor device according to claim 1 .
4. A NOT circuit comprising the semiconductor device according to claim 1 .
5. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a latch circuit, and a memory circuit,
wherein:
the memory circuit comprises first and second memory elements,
each of the first and second memory elements comprises a fifth transistor containing an oxide semiconductor in a channel thereof, a sixth transistor, and a capacitor,
in each of the first and second memory elements,
one of a source and a drain of the fifth transistor is electrically connected to the capacitor and a gate of the sixth transistor, and
the other of the source and the drain of the fifth transistor and one of a source and a drain of the sixth transistor are electrically connected to the latch circuit,
gates of the fifth transistors in the first and second memory elements are electrically connected to each other,
each of the first transistor and the second transistor is an n-channel transistor,
each of the third transistor and the fourth transistor is a p-channel transistor,
one of a source and a drain of the first transistor is supplied with a low power supply voltage,
the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
the other of the source and the drain of the second transistor is electrically connected to the latch circuit and one of a source and a drain of the third transistor,
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
the other of the source and the drain of the fourth transistor is supplied with a high power supply voltage,
a gate of the first transistor is electrically connected to a gate of the fourth transistor,
a gate of the second transistor is electrically connected to a gate of the third transistor, and
the memory circuit is configured to store data stored in the latch circuit, while supply of a power supply voltage is stopped.
6. The semiconductor device according to claim 5 , wherein the memory circuit comprises a transistor comprising a metal oxide in a channel formation region.
7. A buffer circuit comprising the semiconductor device according to claim 5 .
8. A NOT circuit comprising the semiconductor device according to claim 5 .