Setup and method for noise parameter measurement
View Patent ↗A noise parameter test setup allows accurately measuring the four noise parameters (Fmin, Rn, ┌opt) of microwave transistors over a wide frequency range using two distinct wideband measurement paths, based on differential wafer probes, instead of SPDT switches, to commute between s-parameter (signal) measurement and noise measurement path, avoiding thus the uncertainty of the accuracy as well limited availability of SPDT switches. Calibration of the system is the same as when using switches, when hopping the DUT chip from one set or subset of probes to the next. Additional power control precautions of the VNA sources are necessary to avoid injecting signal power into the sensitive noise receiver during s-parameter measurements and jamming the weak noise power during noise measurement.
1. An on-wafer noise parameter measuring system, being controlled by a computer, for measuring noise parameters and s-parameters of a semiconductor chip on a wafer comprising: a measurement setup,
wherein the measurement setup comprises
a noise measurement path for measuring the noise parameters of the chip, and
an s-parameter measurement path for measuring s-parameters of the chip,
said noise measurement path including,
a cascade of calibrated noise source, input impedance tuner, input DC bias network, a first subset of wafer probes, output DC bias network, noise receiver and RF cables;
and said s-parameter measurement path including,
a second subset of wafer probes, input and output DC bias networks, RF cables and a vector network analyzer connected to the second subset of wafer probes,
and wherein
the bias networks of both paths are connected to DC bias supplies.
2. The measurement setup of claim 1 ,
wherein
both subsets of wafer probes are combined in one set of differential (G1-S1-G2-S2-G3) bias-able probes and there are no external bias-tees,
and wherein
probe tips G1-S1-G2 are part of the noise measurement path and probe tips G2-S2-G3 are part of the s-parameter measurement path.
3. The measurement setup of claim 1 , wherein at least the wafer-probe on the source side of the noise measurement path is not bias-able and a bias-tee is inserted between the noise source and the tuner.
4. The measurement setup of claim 2 or claim 3 , wherein the network analyzer, tuner, bias supplies and noise receiver are operationally controlled by a system computer.
5. The measurement setup of claim 4 , wherein all wafer probes are single ended non-bias-able probes and bias-tees are inserted in the associated measurement paths.
6. A noise parameter measurement method for a multitude of frequencies, performed using the apparatus of claim 1 ,
the said method comprising the following steps:
a) calibrate the setup for the multitude of frequencies;
b) connect a DUT (chip) to the second subset of wafer probes;
c) apply DC bias to the chip;
d) measure s-parameters of the chip for at least part of the multitude of frequencies and save;
e) switch off the DC bias;
f) break contact;
g) connect the chip to the first subset of wafer probes and apply DC bias as in step (c);
h) in a source admittance loop (SAL), comprising a multitude of source admittances, nested inside a frequency loop (FL), comprising frequencies as in step (d), execute the following steps:
h1) set the first frequency in the FL loop;
h2) step through the admittances of the source admittance (SAL) loop;
h2.1) for each source admittance measure noise figure;
h2.2) save the noise figure measurement data;
h3) after termination of the source admittance (SAL) loop, extract the noise parameters and save;
h4) set the next frequency in the FL loop;
h5) go to step (h2);
h6) terminate if the frequency loop (FL) ends;
i) move to next chip (step (b)).
7. A noise parameter measurement method for a multitude of frequencies, performed using the apparatus of claim 1 ,
the said method comprising the following steps:
a) calibrate the setup for the multitude of frequencies;
b) connect a DUT (chip) to the second subset of wafer probes;
c) apply DC bias to the chip;
d) measure s-parameters of the chip for the multitude of frequencies and save;
e) switch off the DC bias;
f) break contact;
g) connect the chip to the first subset of wafer probes and apply DC bias as in step (c);
h) in a frequency loop, comprising at least part of the multitude of frequencies, nested inside a source admittance loop (SAL), comprising a multitude of source admittances, execute the following steps:
h1) set the first admittance of the SAL loop;
h2) step through the frequencies of the frequency loop;
h2.1) for each frequency measure and save the noise figure;
h3) after termination of the frequency loop
h5) set the next admittance in the SAL loop;
h5) go to step (h2);
h6) terminate if the source admittance loop SAL ends;
h7) calculate the noise parameters of the chip for the frequencies of the frequency loop;
i) move to next chip (step (b)).