IP Library Patent Application 15654903
Patent Application
App. No. 15/654,903

Fabrication Method OF A Package Substrate

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Quick Facts
Patent No.
US None
App. No.
15/654,903
Abstract

This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first wiring layer including at least one first metal wire; a conductive connecting unit including a first connecting unit and a second connecting unit on the first wiring layer; a circuit chip having at least one connection terminal and disposed on the first connecting unit; a molding compound layer covering the wiring layer, the conductive connecting unit and the circuit chip; and a second wiring layer including at least one second metal wire and connected to the second connecting unit; wherein the first connecting unit is configured for connecting one of the at least one connection terminal with one of the at least one first metal wire.

Claims (11)

1 . A method for fabricating a package substrate, comprising steps of:

(A) providing a carrier;

(B) forming a first wiring layer on the carrier while enabling the first wiring layer to be formed including at least one first metal wire;

(C) forming a conductive connecting unit including a first connecting unit and a second connecting unit on the first wiring layer;

(D) providing a circuit chip having at least one connection terminal to be disposed on the first connecting unit while enabling the first connecting unit to connect one of the at least one connection terminal with one of the at least one first metal wire and a space to be formed between the circuit chip and the carrier;

(E) forming a molding compound layer on the first wiring layer while enabling the molding compound layer to cover the first wiring layer, the conductive connection unit and the circuit chip.

2 . The method of claim 1 , wherein the first connecting unit includes a metal pillar.

3 . The method of claim 1 , wherein the first connecting unit includes a solder bump.

4 . The method of claim 1 , further comprising:

(F1) removing a portion of the molding compound layer so that a top surface of the circuit chip is exposed; and

(F2) removing the carrier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2018
From: PHOENIX PIONEER TECHNOLOGY CO., LTD.
To: PHOENIX & CORPORATION
Reel/Frame 044724/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2017
From: HU, CHU-CHIN; HSU, SHIH-PING; LIU, CHIN-MING
To: PHOENIX PIONEER TECHNOLOGY CO., LTD.
Reel/Frame 043268/0171 →