Dynamic determination of threshold power level for use in distinguishing between downlink and uplink periods in time-division duplexed (TDD) communications
Dynamic determination of threshold power level for use in distinguishing between downlink and uplink periods in time-division duplexed (TDD) communications. For example, downlink and uplink periods may be distinguished in TDD communications in a distributed communications system (DCS), such as a distributed antenna system (DAS). Detecting a power level in a TDD communications signal less than the threshold power level is used to identify uplink periods in the TDD communications signal. In this manner, TDD communications circuits involved with transmitting TDD communications signals can synchronize their transmission circuitry to only transmit downlink TDD communications signals in downlink periods and receive uplink TDD communications signals in uplink periods. The threshold power level used to distinguish between downlink and uplink periods in a TDD communications signal can also be dynamically determined to avoid mistakenly identifying an uplink period during a true downlink period in the TDD communications signals.
1. A time-division duplexed (TDD) detection circuit, comprising:
a power detector circuit configured to:
detect a power level in a TDD communications signal; and
generate a power level signal indicating the detected power level in the TDD communications signal; and
a processing circuit configured to:
sample the power level signal at a sampling rate into a plurality of power level samples;
divide the plurality of power level samples into a plurality of power level sample blocks;
determine an average power level in each of the plurality of power level sample blocks;
determine a power level sample block among the plurality of power level sample blocks having a lowest average power level; and
generate a threshold power level signal indicating a threshold power level based on the average power level in the power level sample block determined to have the lowest average power level.
2. The TDD detection circuit of claim 1 , further comprising:
a TDD communications signal input configured to receive the TDD communications signal; and
wherein:
the power detector circuit comprises a power detector input communicatively coupled to the TDD communications signal input, and a power detector output, the power detector circuit configured to:
detect the power level in the TDD communications signal on the TDD communications signal input; and
generate the power level signal on the power detector output indicating the detected power level in the TDD communications signal; and
the processing circuit comprising a processing circuit input communicatively coupled to the power detector output and a processing circuit output, the processing circuit configured to:
sample the power level signal on the processing circuit input at the sampling rate into the plurality of power level samples; and
generate the threshold power level signal indicating the threshold power level on the processing circuit output based on the power level sample block determined to have the lowest average power level.
3. The TDD detection circuit of claim 1 , further comprising a storage circuit configured to store the threshold power level based on the threshold power level signal.
4. The TDD detection circuit of claim 1 , further comprising a comparator circuit configured to:
compare the threshold power level signal with a detected power level signal in the TDD communications signal; and
generate a comparator output signal indicating a difference between the threshold power level signal and the detected power level signal in the TDD communications signal.
5. The TDD detection circuit of claim 1 , wherein a TDD communications signal interface comprises a communications interface configured to receive a downlink TDD communications signal.
6. The TDD detection circuit of claim 1 , wherein:
the power detector circuit is configured to generate the power level signal comprising a power level voltage signal indicating the detected power level in the TDD communications signal; and
the processing circuit is configured to:
sample the power level voltage signal at the sampling rate into the plurality of power level samples comprising a plurality of power level voltage samples;
divide the plurality of power level voltage samples into the plurality of power level sample blocks;
determine the power level sample block among the plurality of power level sample blocks having the lowest average power level; and
generate the threshold power level signal comprising a threshold power level voltage signal based on the average power level in the power level sample block determined to have the lowest average power level.
7. The TDD detection circuit of claim 1 , wherein:
the processing circuit is further configured determine a maximum power level in the TDD communications signal; and
the processing circuit is configured to generate the threshold power level signal indicating the threshold power level based on a difference between the average power level in the power level sample block determined to have the lowest average power level and the determined maximum power level.
8. The TDD detection circuit of claim 7 , wherein the processing circuit is configured to generate the threshold power level signal indicating the threshold power level as: approximately half of the difference between the average power level in the power level sample block determined to have the lowest average power level and the determined maximum power level, added to the average power level in the power level sample block determined to have the lowest average power level.
9. The TDD detection circuit of claim 1 , wherein the processing circuit is configured to sample the power level signal at the sampling rate less than a symbol rate of the TDD communications signal into the plurality of power level samples.
10. The TDD detection circuit of claim 1 , wherein the sampling rate is approximately 50 microseconds (μs) and a symbol rate is either approximately 71.4 μs or 83.3 μs.
11. The TDD detection circuit of claim 1 , wherein a number of plurality of power level sample blocks is at least twice a number of radio sub-frames in the TDD communications signal.
12. The TDD detection circuit of claim 1 , wherein a number of the plurality of power level sample blocks is 20 and a number of radio sub-frames in the TDD communications signal is 10.
13. The TDD detection circuit of claim 1 , wherein a number of the plurality of power level sample blocks is 20 and a number of power level samples in each power level sample block among the plurality of power level sample blocks is 10.
14. A method of determining a threshold power level for distinguishing between downlink and uplink periods in a time-division duplexed (TDD) communications signal, comprising:
(a) generating a power level signal indicating a detected power level in the TDD communications signal;
(b) sampling the power level signal at a sampling rate into a plurality of power level samples;
(c) dividing the plurality of power level samples into a plurality of power level sample blocks;
(d) determining an average power level in each of the plurality of power level sample blocks;
(e) determining a power level sample block among the plurality of power level sample blocks having a lowest average power level; and
(f) generating a threshold power level signal indicating a threshold power level based on the average power level in the power level sample block determined to have the lowest average power level.
15. The method of claim 14 , further comprising detecting a power level in the TDD communications signal.
16. The method of claim 14 , further comprising storing the threshold power level indicated by the threshold power level signal.
17. The method of claim 14 , further comprising:
comparing the threshold power level signal with a detected power level signal in the TDD communications signal; and
generating a comparator output signal indicating a difference between the threshold power level signal and the detected power level signal in the TDD communications signal.
18. The method of claim 14 , further comprising:
determining a maximum power level in the TDD communications signal; and
generating the threshold power level signal comprising generating the threshold power level signal indicating the threshold power level based on a difference between the average power level in the power level sample block determined to have the lowest average power level and the determined maximum power level.
19. The method of claim 18 , wherein generating the threshold power level signal indicating the threshold power level comprises:
determining the difference between the average power level in the power level sample block determined to have the lowest average power level and the determined maximum power level;
dividing the determined difference by approximately half to provide a divided difference;
adding the average power level in the power level sample block determined to have the lowest average power level to the divided difference to provide the threshold power level signal.
20. The method of claim 14 , comprising sampling the power level signal at the sampling rate less than a symbol rate of the TDD communications signal into the plurality of power level samples.
21. The method of claim 14 , wherein a number of plurality of power level sample blocks is at least twice a number of radio sub-frames in the TDD communications signal.
22. The method of claim 14 , comprising repeatedly performing steps (a)-(f).