SOI WAFERS AND DEVICES WITH BURIED STRESSOR

1 . A semiconductor structure comprising a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers.

2 . The semiconductor structure of claim 1 , wherein the BS layer comprises silicon germanium.

3 . The semiconductor structure of claim 2 , wherein the BL layer comprises substantially pure silicon.

4 . The semiconductor structure of claim 3 , wherein the silicon BL is a monolayer of silicon.

5 . The semiconductor structure of claim 3 , wherein the silicon BL is approximately one or two nm thick.

6 . The semiconductor structure of claim 3 , further comprising one or more trenches of a depth sufficient to pass through the SOI, BOX, BL, and BS layers and into the underlying silicon, the trenches filled with an oxide.

7 . The semiconductor structure of claim 6 , wherein the oxide is a silicon oxide.

8 . An active device having a channel formed in the SOI layer of the silicon structure of claim 1 .

9 . A method for forming a semiconductor structure with a buried stressor (BS) layer having a bonding layer (BL) at its surface, the method comprising:

forming the BS layer on a substrate of a first wafer;

growing the BL layer at the surface of the BS layer; and

wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer.

10 . The method of claim 9 , wherein the BS layer is silicon germanium and the substrate of the first wafer is silicon or a semiconductor alloy containing silicon, and the BS layer is grown epitaxially on the substrate of the first wafer.

11 . The method of claim 10 , wherein the BS layer is grown to a thickness less than a critical thickness, at which misfit dislocations are generated.

12 . The method of claim 10 , wherein the BS layer is grown to a thickness in the range 5 nm to 70 nm.

13 . The method of claim 10 , wherein the BL is formed by epitaxial growth on top of the BS layer, and is grown to a monolayer thick.

14 . The method of claim 10 , wherein the BL is formed by epitaxial growth on top of the BS layer, and is grown to approximately one or two nm thick.

15 . The method of claim 10 , wherein the silicon oxide layer of the second wafer is formed on the silicon substrate of the second layer to a thickness in the range 5 nm to 80 nm.

16 . The method of claim 9 , wherein the BS layer is silicon germanium of non-uniform germanium concentration throughout its thickness.

17 . The method of claim 9 , further comprising removing a majority of thickness of the substrate of the second wafer, leaving a layer of silicon having a thickness in the range 0.2 nm to 50 nm remaining on the silicon oxide layer, and the silicon oxide layer bonded to the BL layer above the BS layer of the first wafer.

18 . The method of claim 17 , wherein the BS layer is silicon germanium and the substrate of the first wafer is silicon or a semiconductor alloy containing silicon, and the BS layer is grown epitaxially on the substrate of the first wafer.

19 . The method of claim 18 , further comprising patterning the semiconductor structure and etching trenches therein such that the trenches are of a depth sufficient to pass through the silicon oxide, BL, and BS layers and into the substrate of the first wafer, and filling the trenches with an oxide.

20 . The method of claim 9 , further comprising annealing the semiconductor structure after wafer bonding the first wafer to the second wafer.