Multi mode interface and detection circuit
A communication interface circuit includes a plurality of terminals, two receiver circuits, and a detection circuit. The detection circuit is coupled to at least one of the terminals and detects a communication format, and the detection circuit enables one of the two receiver circuits based on the detected communication format.
1. A communication interface circuit comprising:
a plurality of terminals to receive a communication, the plurality of terminals including a first terminal and a second terminal;
a first receiver circuit coupled to the plurality of terminals, the first receiver circuit being configured to receive a first communication format;
a second receiver circuit coupled to the plurality of terminals, the second receiver circuit being configured to receive a second communication format; and
an interface detection circuit coupled to at least one of the plurality of terminals and coupled to the first receiver circuit and the second receiver circuit, the interface detection circuit configured to detect a frequency of a first signal received at the first terminal, determine whether the communication received by the plurality of terminals is in one of the first communication format and the second communication format based on the detected frequency of the first signal, and enable one of the first receiver circuit and the second receiver circuit based on the determination.
2. The communication interface circuit of claim 1 wherein the interface detection circuit is further configured to detect at least one of an impedance and a voltage of a second signal received at the second terminal of the plurality of terminals.
3. The communication interface circuit of claim 2 wherein the interface detection circuit is further configured to compare the detected impedance or voltage level to a threshold to further determine the first communication format and the second communication format.
4. The communication interface circuit of claim 1 wherein the first receiver circuit is configured to receive parallel data communication and the second receiver circuit is configured to receive serial data communication.
5. The communication interface circuit of claim 1 wherein the interface detection circuit is configured to enable one of the first receiver circuit and the second receiver circuit by default when the interface detection circuit cannot determine whether the communication received by the plurality of terminals is in one of the first communication format and the second communication format.
6. The communication interface circuit of claim 1 wherein the interface detection circuit is configured with a bias toward enabling one of the first receiver circuit and the second receiver circuit.
7. The communication interface circuit of claim 1 wherein the interface detection circuit is configured with a delay, the delay enforcing an amount of time the determination must remain unchanged before the interface detection circuit enables one of the first receiver circuit and the second receiver circuit based on the determination.