Semiconductor package and fabrication method thereof

1. A semiconductor package comprising:

a substrate;

a semiconductor chip disposed on the substrate, the semiconductor chip including a passivation layer, an active surface, an inactive surface and a side surface, wherein the passivation layer is disposed on the active surface, wherein the active surface is opposite to the inactive surface, wherein the active surface faces the substrate, wherein the side surface includes a side step or a side slope and is extended from an edge of the passivation layer to the inactive surface, and wherein a first width of the active surface is smaller than a second width of the inactive surface; and

an underfill which is interposed between the substrate and the passivation layer of the semiconductor chip.

2. The semiconductor package of claim 1 , wherein the underfill is extended to the side step or the side slope of the semiconductor chip.

3. The semiconductor package of claim 1 , wherein the underfill is inclined in an upward direction toward the inactive surface from the active surface of the semiconductor chip.

4. The semiconductor package of claim 1 , wherein the substrate is an interposer.

5. The semiconductor package of claim 1 , further comprising a micro cooling channel provided at the side step or the side slope.

6. The semiconductor package of claim 1 , further comprising a connection member disposed between the semiconductor chip and the substrate,

wherein the underfill covers a lateral surface of the connection member.

7. The semiconductor package of claim 6 , wherein the semiconductor chip further comprises a conductive pad on the active surface and is electrically connected to the connection member.

8. The semiconductor package of claim 1 , wherein the active surface and the passivation layer have substantially the same widths.

9. The semiconductor package of claim 1 , wherein the side step or the side slope of the side surface is extended from the edge of the passivation layer.

10. A semiconductor package comprising:

a substrate;

a plurality of semiconductor chips disposed on the substrate; and

an underfill,

wherein the plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip,

wherein the first semiconductor chip includes a first active surface, a first inactive surface and a first side surface,

wherein the second semiconductor chip includes a second active surface, a second inactive surface and a second side surface,

wherein the second active surface of the second semiconductor chip faces the first inactive surface of the first semiconductor chip,

wherein the second side surface of the second semiconductor chip includes a side step or a side slope and is formed from the second active surface of the second semiconductor chip to the second inactive surface of the second semiconductor chip,

wherein a first width of the second active surface of the second semiconductor chip is smaller than a second width of the second inactive surface of the second semiconductor chip, and

wherein the underfill is disposed between the second active surface of the second semiconductor chip and the first inactive surface of the first semiconductor chip.

11. The semiconductor package of claim 10 , wherein the underfill is extended to the side step or the side slope of the second side surface of the second semiconductor chip.

12. The semiconductor package of claim 11 , wherein the underfill is inclined in an upward direction toward the second inactive surface from the second active surface of the second semiconductor chip.

13. The semiconductor package of claim 10 , further comprising:

a through-silicon via provided in the first semiconductor chip; and

a connection member connected to the through-silicon via,

wherein the connection member is between the second active surface of the second semiconductor chip and the first inactive surface of the first semiconductor chip.

14. The semiconductor package of claim 13 , wherein the first semiconductor chip further includes an upper pad between the connection member and the first inactive surface,

wherein the second semiconductor chip further includes a lower pad between the connection member and the second active surface, and

wherein the upper pad and the lower pad do not overlap the side step or the side slope of the second side surface of the second semiconductor chip.

15. The semiconductor package of claim 10 , further comprising a micro cooling channel provided at the side step or the side slope.

16. The semiconductor package of claim 10 , wherein the second semiconductor chip is bonded to the first semiconductor chip by the underfill, and

wherein the underfill is positioned at an inner side of an edge of the second semiconductor chip.

17. A semiconductor package comprising:

a substrate;

a semiconductor chip including an inactive surface, an active surface opposite to the inactive surface, and a side surface between the inactive surface and the active surface, the side surface including a stepped portion and extending from an edge of the active surface to an edge of the inactive surface; and

an underfill which is provided between the substrate and a passivation layer of the semiconductor chip,

wherein the stepped portion of the side surface includes a first lateral surface extending from the edge of the active surface and a second lateral surface extending from the edge of the inactive surface,

wherein at least a portion of the first lateral surface is substantially perpendicular to the active surface, and wherein at least a portion of the second lateral surface is substantially perpendicular to the inactive surface; and

wherein a first width of the active surface is smaller than a second width of the inactive surface.

18. The semiconductor package of claim 17 , wherein the side surface includes the stepped portion, and the underfill extends to the stepped portion.

19. The semiconductor package of claim 17 , wherein the passivation layer is disposed on the active surface, and

wherein the active surface and the passivation layer have substantially the same widths.