Dynamic termination edge control

1. A semiconductor device comprising:

a command interface configured to receive a command to assert on-die termination (ODT) during an operation;

an input configured to receive an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward direction;

a delay pipeline configured to delay the received command the number of shifts in the backward direction to generate a shifted rising edge command signal; and

combination circuitry configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

2. The semiconductor device of claim 1 , wherein the transformed command comprises a shifted and stretched version of the received command.

3. The semiconductor device of claim 1 , comprising an additional input configured to receive an indication of an additional shift mode register value that corresponds to a number of shifts of a falling edge of the command in a forward direction, wherein the delay pipeline is configured to delay the received command the number of shifts in the forward direction.

4. The semiconductor device of claim 1 , wherein the combination circuitry comprises an OR gate.

5. The semiconductor device of claim 1 , wherein a maximum value for the number of shifts in the backward direction is set by a maximum value representable in a shift mode register holding the shift mode register value.

6. The semiconductor device of claim 1 , wherein a maximum value for the number of shifts in the backward direction is limited to prevent interference with an adjacent operation.

7. The semiconductor device of claim 6 , wherein the operation comprises a write operation.

8. The semiconductor device of claim 7 , wherein the adjacent operation comprises a read operation, a non-target read operation, or a non-target write operation.

9. The semiconductor device of claim 1 , wherein the delay pipeline is configured to generate a plurality of backward shifted commands relative to a default command, wherein the default command comprises an unshifted command that is delayed through the delay pipeline by a maximum number of possible shifts in the backward direction to cause the backward shifted commands that are delayed less in the delay pipeline to be backward in time relative to the default command.

10. A semiconductor device comprising:

a command interface configured to receive a command to assert on-die termination (ODT) during an operation;

a first input configured to receive an indication of a backward shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward direction;

a second input configured to receive an indication of a forward shift mode register value that corresponds to a number of shifts of a falling edge of the command in a forward direction;

a delay pipeline configured to produce a plurality of shifted commands by delaying the received command a maximum number of shifts in the backward direction to generate a plurality of rising edge command signals and a maximum number of shifts in the forward direction to generate a plurality of falling edge command signals;

selection circuitry to select a selected rising edge command signal based on the first input and to select a selected falling edge command signal based on the second input; and

combination circuitry to combine the selected rising edge command signal with the selected falling edge command signal to form a transformed command.

11. The semiconductor device of claim 10 , wherein the transformed command comprises a shifted and stretched version of the received command.

12. The semiconductor device of claim 10 , wherein the selection circuitry is configured to select, as the selected rising edge command signal or the selected falling edge command signal, an unshifted command that has been shifted by the maximum number of shifts in the forward direction based on the first input.

13. The semiconductor device of claim 10 , wherein the combination circuitry comprises an OR gate configured to combine the selected rising edge command signal with selected falling edge command signal.

14. The semiconductor device of claim 10 , wherein the delay pipeline comprises a plurality of flip-flops that are connected to a common clock.

15. The semiconductor device of claim 10 , wherein the maximum number of shifts in the forward direction is the same as the maximum number of shifts in the backward direction.

16. The semiconductor device of claim 10 , wherein a default unshifted command is delayed in the delay pipeline by a maximum number of shifts in the backward direction.

17. A method, comprising:

receiving a command to assert on-die termination (ODT) on a semiconductor device during an operation;

shifting the command in a delay pipeline to form a plurality of shifted commands, wherein shifting the command comprises:

shifting the command in a backward direction by delaying a default command to cause backward shifted commands of the plurality of shifted commands to be shifted backward relative to the delayed default command by shifting the backward shifted commands through the delay pipeline by a fewer number of delays to occur earlier than the default command; and

shifting forward shifted commands of the plurality of shifted commands in a forward direction relative to the delayed default command;

receiving a backward shift mode register value indicating how far to shift a rising edge of the command in the backward direction using the delay pipeline;

selecting a first shifted command of the plurality of shifted commands as a selected rising edge command signal based on the backward shift mode register value;

receiving a forward shift mode register value indicating how far to shift a falling edge of the command in the forward direction using the delay pipeline;

selecting a second shifted command of the plurality of shifted commands as a selected falling edge command signal based on the forward shift mode register value; and

combining the selected rising edge command signal and the selected falling edge command signal to form a shifted and stretched command.

18. The method of claim 17 , wherein shifting the command comprises delaying the command by a delay number that is equal to a maximum number of shifts in the forward direction and a maximum number of shifts in the backward direction.

19. The method of claim 18 , wherein shifting the command comprises delaying the command using the delay number of flip flops.

20. The method of claim 19 , wherein the plurality of shifted commands comprises the delay number of shifted commands plus one.