IP Library Granted Patent US 10,534,725
Granted Patent B2
US 10,534,725 · App. 15/658,441 · Granted Jan 14, 2020

Computer system software/firmware and a processor unit with a security module

Inventors: Angel Nunez Mencias (Stuttgart, DE); Jakob C. Lang (Weil im Schoenbuch, DE); Martin Recktenwald (Schoenaich, DE); Ulrich Mayer (Weil im Schoenbuch, DE)
Assignee: International Business Machines Corporation
G06F12/1408G06F13/24G06F2212/1052
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Quick Facts
Patent No.
US 10,534,725
App. No.
15/658,441
Granted
Jan 14, 2020
Kind
B2
Abstract

Technology for decrypting and using a security module in a processor cache in a secure mode such that dynamic address translation prevents access to portions of the volatile memory outside of a secret store in a volatile memory.

Claims (57)

1. A computer program product for use with a security module including program instructions for providing a secret store in a volatile memory for secret data and an interface for interacting with an operating system, the computer program product comprising:

a machine readable storage device; and

computer code stored on the machine readable storage device, with the computer code including instructions for causing a processor(s) set to perform operations including the following:

storing, in a processor cache included in a processor, data constituting the security module in an encrypted form that can be decrypted by a secret key,

switching the processor to a secure mode,

responsive to the switching to the secure mode, disabling a write operation, with the write operation being an operation that writes the data constituting the security module from the processor cache to a volatile memory,

decrypting, in the processor cache, the data constituting the security module with the secret key,

configuring dynamic address translation to prevent access to portions of the volatile memory outside of the secret store,

receiving data through the interface of the security module,

encrypting, by the security module and in the processor cache, the data received through the interface of the security module using a public key,

enabling the write operation, and

switching the processor to a normal operating system mode;

wherein the processor cache included in the processor includes:

a first level instruction cache included in the processor;

a first level data cache included in the processor;

a second level instruction cache included in the processor; and

a second level data cache included in the processor.

2. The computer program product of claim 1 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

disabling the write operation for data tagged with a non-secure flag.

3. The computer program product of claim 1 wherein the interface of the security module is in the form of an application programming interface using a crypto architecture.

4. The computer program product of claim 1 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

receiving, by the processor, an interrupt request;

responsive to the interrupt request, suspending execution of the security module; and

subsequent to the encryption of the security module, passing control to an interrupt handling program.

5. The computer program product of claim 4 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

terminating the interrupt request; and

responsive to the termination of the interrupt request, restarting the security module.

6. The computer program product of claim 1 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

sharing the security module between a plurality of programs using a semaphore mechanism to serialize access to the secret store of the volatile memory.

7. A computer system for use with a security module including program instructions for providing a secret store in a volatile memory for secret data and an interface for interacting with an operating system, the computer system comprising:

a processor(s) set;

a machine readable storage device; and

computer code stored on the machine readable storage device, with the computer code including instructions for causing the processor(s) set to perform operations including the following:

storing, in a processor cache included in a processor, data constituting the security module in an encrypted form that can be decrypted by a secret key,

switching the processor to a secure mode,

responsive to the switching to the secure mode, disabling a write operation, with the write operation being an operation that writes the data constituting the security module from the processor cache to a volatile memory,

decrypting, in the processor cache, the data constituting the security module with the secret key,

configuring dynamic address translation to prevent access to portions of the volatile memory outside of the secret store,

receiving data through the interface of the security module,

encrypting, by the security module and in the processor cache, the data received through the interface of the security module using a public key,

enabling the write operation, and

switching the processor to a normal operating system mode;

wherein the processor cache included in the processor includes:

a first level instruction cache included in the processor;

a first level data cache included in the processor;

a second level instruction cache included in the processor; and

a second level data cache included in the processor.

8. The computer system of claim 7 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

disabling the write operation for data tagged with a non-secure flag.

9. The computer system of claim 7 wherein the interface of the security module is in the form of an application programming interface using a crypto architecture.

10. The computer system of claim 7 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

receiving, by the processor, an interrupt request;

responsive to the interrupt request, suspending execution of the security module; and

subsequent to the encryption of the security module, passing control to an interrupt handling program.

11. The computer system of claim 10 wherein the computer code further includes instructions for causing the processor(s) set to perform the following operations:

terminating the interrupt request; and

responsive to the termination of the interrupt request, restarting the security module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2017
From: NUNEZ MENCIAS, ANGEL; LANG, JAKOB C.; RECKTENWALD, MARTIN; MAYER, ULRICH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 043084/0810 →
Continuity (1)
Related Publication 20190034356A1 · Jan 31, 2019