Heat transfer structures and methods for IC packages

1. A package structure comprising:

a first package layer comprising an electrical signal structure and a first thermal conduction structure electrically isolated from the electrical signal structure;

a second package layer comprising a second thermal conduction structure; and

a chip layer positioned between the first package layer and the second package layer, the chip layer comprising:

an integrated circuit (IC) chip electrically connected to the electrical signal structure;

a molding material; and

a through-via positioned in the molding material,

wherein the first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.

2. The package structure of claim 1 , wherein

the through-via is one through-via of a plurality of through-vias, and

the low thermal resistance path from the IC chip to the surface of the second package layer includes the plurality of through-vias being configured in parallel.

3. The package structure of claim 1 , wherein the first thermal conduction structure comprises redistribution lines.

4. The package structure of claim 1 , wherein the second thermal conduction structure comprises redistribution lines.

5. The package structure of claim 1 , further comprising a heat spreader positioned at the surface of the second package layer.

6. The package structure of claim 1 , further comprising a printed circuit board electrically connected to the electrical signal structure.

7. The package structure of claim 1 , wherein the IC chip comprises an on-chip thermal conduction structure having a low thermal resistance interface to the first thermal conduction structure.

8. The package structure of claim 1 , wherein the IC chip and the electrical signal structure are part of an integrated voltage regulator.

9. The package structure of claim 1 , wherein the electrical signal structure comprises an inductive device.

10. The package structure of claim 1 , wherein the package structure is part of an integrated fan-out package.

11. The package structure of claim 1 , wherein the IC chip comprises:

a first device, and

a second device.

12. A package structure comprising:

a printed circuit board (PCB);

a first package layer over the PCB, the first package layer comprising:

an electrical signal structure electrically connected to the PCB; and

a first thermal conduction structure electrically isolated from the electrical signal structure;

a second package layer over the first package layer, the second package layer comprising a second thermal conduction structure electrically isolated from the electrical signal structure; and

a chip layer positioned between the first package layer and the second package layer, the chip layer comprising:

an integrated circuit (IC) chip electrically connected to the electrical signal structure;

a molding material; and

a set of through-vias positioned in the molding material and the second package layer,

wherein the first thermal conduction structure, the set of through-vias, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.

13. The package structure of claim 12 , further comprising:

a set of under-bump metallurgies (UBMs) positioned between the PCB and the electrical signal structure.

14. The package structure of claim 12 , further comprising:

a heat spreader positioned at the surface of the second package layer.

15. The package structure of claim 12 , wherein

the package structure is part of an integrated fan-out package,

the first thermal conduction structure comprises a first set of post-passivation interconnect (PPI) structures, and

the second thermal conduction structure comprises a second set of PPI structures.