IP Library › Granted Patent US 10,241,151
Granted Patent B2
US 10,241,151 · App. 15/659,727 · Granted Mar 26, 2019

Die crack detector and method therefor

Inventors: Audel Sanchez (Tempe, AZ); Jose Luis Suarez (Chandler, AZ); Michele Lynn Miera (Chandler, AZ)
Assignee: NXP USA, INC.
G01R31/2896G01R31/025H01L23/5223H01L23/585H01L24/48H01L28/40H01L2224/4823H01L2224/48227H01L2924/1205
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Quick Facts
Patent No.
US 10,241,151
App. No.
15/659,727
Granted
Mar 26, 2019
Kind
B2
Abstract

A die crack detector and method are provided. A first metal trace is formed over a substrate with the first metal trace configured to extend around a perimeter of a semiconductor die. A second metal trace is formed over the first metal trace with the second metal trace configured to overlap the first metal trace. A dielectric material is disposed between the first and second metal traces. A first detector terminal is coupled to the first metal trace and a second detector terminal coupled to the second metal trace. The detector terminals are configured to receive a predetermined voltage.

Claims (38)

1. A die crack detector comprising:

a first metal trace formed over a substrate, the first metal trace configured to substantially extend around a perimeter of a semiconductor die;

a second metal trace formed over the first metal trace, the second metal trace configured to at least substantially overlap the first metal trace;

a dielectric material disposed between the first metal trace and the second metal trace;

a first detector terminal coupled to the first metal trace, the first detector terminal configured to receive a first power supply voltage; and

a second detector terminal coupled to the second metal trace, the second detector terminal configured to receive a second power supply voltage.

2. The die crack detector of claim 1 , wherein the first metal trace is configured to form a first contiguous ring around the perimeter of the semiconductor die, and wherein the second metal trace is configured to form a second contiguous ring overlapping the first contiguous ring, the first and second contiguous rings enclosing functional circuitry.

3. The die crack detector of claim 1 , wherein the second terminal is coupled to a package pin to receive the second power supply voltage.

4. The die crack detector of claim 1 , wherein the dielectric material is characterized as a silicon nitride (SiN) material.

5. The die crack detector of claim 1 , wherein the first metal trace, the dielectric material, and the second metal trace form a metal-insulator-metal (MIM) capacitor.

6. The die crack detector of claim 5 , wherein the second power supply voltage is a predetermined voltage, the predetermined voltage lower than a breakdown voltage of the MIM capacitor.

7. The die crack detector of claim 6 , further comprising a first power supply having a first terminal coupled to provide a ground voltage at the first detector terminal and a second terminal coupled to provide the predetermined voltage at the second detector terminal.

8. The die crack detector of claim 7 , further comprising a current measuring device coupled to the first power supply, the current measuring device configured to measure a leakage current while the predetermined voltage is provided at the second detector terminal.

9. The die crack detector of claim 8 , wherein the second terminal is coupled to provide the predetermined voltage at the second detector terminal and the current measuring device is configured to measure the leakage current during a test mode.

10. A die crack detector comprising:

a metal-insulator-metal (MIM) capacitor structure comprising:

a first metal trace formed over a substrate, the first metal trace arranged to at least substantially extend around a perimeter of a semiconductor die,

a second metal trace formed over the first metal trace, the second metal trace arranged to at least substantially overlap the first metal trace, and

a dielectric material disposed between the first metal trace and the second metal trace;

a first detector terminal coupled to the first metal trace, the first detector terminal configured to receive a first power supply voltage; and

a second detector terminal coupled to the second metal trace, the second detector terminal configure to receive a second power supply voltage.

11. The die crack detector of claim 10 , wherein the first metal trace is arranged to form a first contiguous ring around the perimeter of the semiconductor die, and wherein the second metal trace is arranged to form a second contiguous ring overlapping the first contiguous ring.

12. The die crack detector of claim 10 , wherein the second terminal is coupled to a package pin to receive the second power supply voltage.

13. The die crack detector of claim 10 , wherein the dielectric material is characterized as a silicon nitride (SiN) material.

14. The die crack detector of claim 10 , wherein the semiconductor die is characterized as an integrated passive device (IPD).

15. The die crack detector of claim 10 , wherein the first metal trace is formed from a first interconnect layer of the semiconductor die, and wherein the second metal trace is formed from a second interconnect layer of the semiconductor die.

16. The die crack detector of claim 10 , wherein the semiconductor die has a thickness of 3 mils or less.

17. The die crack detector of claim 10 , further comprising a test circuit coupled to the MIM capacitor structure by way of the first and second detector terminals, the test circuit to provide a predetermined test voltage and measure leakage current during a test mode.

18. A method comprising:

providing a metal-insulator-metal (MIM) capacitor structure on a semiconductor die, the MIM capacitor structure comprising:

a first metal trace formed over a substrate of the semiconductor die, the first metal trace arranged to at least substantially extend around a perimeter of the semiconductor die,

a second metal trace formed over the first metal trace, the second metal trace arranged to at least substantially overlap the first metal trace, and

a dielectric material disposed between the first metal trace and the second metal trace;

coupling a test circuit to the first and second metal traces of the MIM capacitor structure;

applying a predetermined test voltage differential across the first and second metal traces of the MIM capacitor structure; and

measuring a leakage current of the MIM capacitor structure while the predetermined test voltage is applied.

19. The method of claim 18 , further comprising determining that the semiconductor die is cracked based on the leakage current exceeding a predetermined test limit.

20. The method of claim 18 , wherein applying the predetermined test voltage and measuring the leakage current are performed by way of the test circuit during a test mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: SANCHEZ, AUDEL; SUAREZ, JOSE LUIS; MIERA, MICHELE LYNN
To: NXP USA, INC.
Reel/Frame 043097/0605 →
Continuity (1)
Related Publication 20190033365A1 · Jan 31, 2019