Program operations in memory
View Patent ↗The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.
1. An apparatus, comprising:
an array of memory cells; and
a controller configured to:
perform a program operation on the array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state; and
apply a second program signal to a second portion of the array of memory cells that are to remain in the second state.
2. The apparatus of claim 1 , wherein the controller is configured to apply the first program signal to a third portion of the array of memory cells that are to change from the second state to the first state.
3. The apparatus of claim 1 , wherein the controller is configured to apply a third program signal to a third portion of the array of memory cells that are to change from the second state to the first state.
4. The apparatus of claim 1 , wherein the controller is configured to apply the second program signal to a third portion of the array of memory cells that are to change from the first state to the second state.
5. The apparatus of claim 1 , wherein the controller is configured to perform the program operation blind.
6. The apparatus of claim 5 , wherein a program signal is applied to each memory cell of the array of memory cells.
7. The apparatus of claim 1 , wherein the controller is configured to perform a pre-read operation on memory cells of the array of memory cells before performing the program operation.
8. The apparatus of claim 7 , wherein the pre-read determines which of the memory cells of the array of memory cells will be programmed during the program operation.
9. The apparatus of claim 1 , wherein the first state is a set state and the second state is a reset state.
10. The apparatus of claim 1 , wherein the first state is a reset state and the second state is a set state.
11. The apparatus of claim 1 , wherein the first program signal is a single uninterrupted signal.
12. An apparatus, comprising:
an array of memory cells; and
a controller configured to:
perform a program operation on the array of memory cells by:
applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state;
applying the first program signal to a second portion of the array of memory cells that are to change from the second state to the first state; and
applying a second program signal to a third portion of the array of memory cells that are to remain in the second state.
13. The apparatus of claim 12 , wherein the controller is configured to apply the second program signal to a fourth portion of the array of memory cells that are to change from the first state to the second state.
14. The apparatus of claim 12 , wherein the first state is a set state and the second state is a reset state.
15. The apparatus of claim 12 , wherein the first state is a reset state and the second state is a set state.
16. The apparatus of claim 12 , wherein the controller is configured to perform the program operation without performing a pre-read operation.
17. The apparatus of claim 12 , wherein the first program signal is a single uninterrupted signal.
18. An apparatus, comprising:
an array of memory cells; and
a controller configured to:
perform a program operation on the array of memory cells by:
applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state;
applying a second program signal to a second portion of the array of memory cells that are to change from the second state to the first state; and
applying a third program signal to a third portion of the array of memory cells that are to change from the first state to the second state and a fourth portion of the array of memory cells that are to remain in the second state.
19. The apparatus of claim 18 , wherein programming from the first state to the second state takes approximately 15 nanoseconds (ns).
20. The apparatus of claim 18 , wherein programming from the second state to the first state takes approximately 500 nanoseconds (ns).
21. A method, comprising:
performing a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state, wherein the first program signal programs memory cells to a second state and then to the first state and wherein performing the program operation includes applying a second program signal to a second portion of the array of memory cells that are to remain in the second state.
22. The method of claim 21 , wherein performing the program operation includes applying the first program signal to a third portion of the array of memory cells that are to change from the second state to the first state.
23. The method of claim 21 , wherein performing the program operation includes applying a third program signal to a third portion of the array of memory cells that are to change from the second state to the first state.
24. The method of claim 21 , wherein performing the program operation includes applying the second program signal to a fourth portion of the array of memory cells that are to change from the first state to the second state.
25. The method of claim 21 , wherein performing the program operation includes applying a program signal to each memory cell of the array of memory cells.
26. The method of claim 21 , wherein performing the program operation includes a pre-read operation to determine which memory cells of the array of memory cells will be programmed during the program operation.
27. The method of claim 21 , wherein the first program signal is a single uninterrupted signal.
28. A method, comprising:
performing a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state and to a second portion of the array of memory cells that are to change from a second state to the first state, wherein the first program signal programs memory cells to the second state and then to the first state and wherein performing the program operation includes applying a second program signal to a third portion of the array of memory cells that are to change from the first state to the second state and a fourth portion of the array of memory cells that are to remain in the second state.
29. The method of claim 28 , wherein the first state is a set state and the second state is a reset state.
30. The method of claim 28 , wherein the first state is a reset state and the second state is a set state.