Apparatuses and methods for indirectly detecting phase variations
View Patent ↗Apparatuses and methods for indirect phase variation detection are disclosed herein. An example apparatus may include a clock generator circuit comprising a delay-locked loop (DLL) circuit configured to adjust a phase of a clock signal based on a phase of a feedback clock signal during an initial phase-lock operation. The DLL circuit includes a phase deviation detection circuit configured to detect a variation in a phase of the clock signal based on variations in gate delays of an oscillation circuit, and to initiate a subsequent phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit.
1. An apparatus, comprising:
a clock generator circuit configured to adjust a phase of a clock signal based on a phase of a feedback clock signal during an initial phase-lock operation, wherein the clock generator circuit comprises a phase deviation detection circuit configured to detect a variation in a phase of the clock signal based on variations in gate delays of an oscillation circuit, and to initiate a subsequent phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit.
2. The apparatus of claim 1 , wherein the phase deviation detection circuit configured to detect variations in the phase of the clock signal based on variations in the gate delays of the oscillation circuit is configured to count oscillations of an oscillation clock signal provided from the oscillation circuit over a predetermined time period to provide a current oscillation count, wherein the phase deviation detection circuit is further configured to compare the current oscillation count with a previous oscillation count to detect variations in the gate delays.
3. The apparatus of claim 2 , wherein the phase deviation detection circuit comprises a control circuit having a plurality of serially-coupled flip-flops to set a predetermined time period.
4. The apparatus of claim 2 , wherein the phase deviation detection circuit comprises a counter circuit having a plurality of flip-flops configured to sequentially latch individual oscillations of the oscillation clock signal provided from the oscillation circuit.
5. The apparatus of claim 2 , wherein the phase deviation detection circuit further comprises a digital compare circuit configured to subtract a larger of the current oscillation count or the previous oscillation count from the smaller of the current oscillation count or the previous oscillation count to provide a difference value and compare the difference value to the predetermined threshold.
6. The apparatus of claim 2 , wherein the phase deviation detection circuit further comprises a first storing circuit configured to store the current oscillation count and a second storing circuit to store the previous oscillation count.
7. The apparatus of claim 6 , wherein the first storing circuit comprises a plurality of flip-flops each configured to store a bit of the current oscillation count.
8. The apparatus of claim 2 , wherein the oscillation circuit comprises a plurality of serially coupled inverters configured to provide the clock signal at an output.
9. The apparatus of claim 8 , wherein the plurality of serially coupled inverters are powered by an external power supply, wherein a variation in the gate delays of the plurality of serially coupled inverters is caused by variation in a voltage of the external power supply.
10. The apparatus of claim 8 , wherein a first subset of the plurality of serially coupled inverters are powered by a first power supply and a second subset of the plurality of serially coupled inverters are powered by a second power supply, wherein a variation in the gate delays of the plurality of serially coupled inverters is caused by variation in a voltage of either the first power supply or the second power supply.
11. An apparatus comprising:
a clock adjusting circuit configured to adjust a phase of a clock signal responsive to assertion of an adjust enable signal; and
a phase deviation detection circuit comprising:
an oscillator configured to output an internal clock signal during a first period of time and a second period of time;
a first storing circuit configured to temporarily store a first count value of the internal clock signal outputted during the first period of time;
a second storing circuit configured to temporarily store a second count value of the internal clock signal outputted during the second period of time; and
a detector configured to compare the first count value and the second count value and to assert the adjust enable signal when a difference between the first and second count value exceeds a threshold value.
12. The apparatus of claim 11 , wherein the phase deviation detection circuit further comprises a period determining circuit configured to determine each of the first period of time and the second period of time based on the clock signal.
13. The apparatus of claim 11 , wherein the first storing circuit is further configured to store the second count value before storing the first count value and the second storing circuit is configured to store the second count value when the first storing circuit stores the first count value.
14. The apparatus of claim 11 , the threshold value is one.
15. The apparatus of claim 11 , the threshold value is variable.
16. A method comprising:
during an initial phase-lock operation, adjusting a phase of a clock signal based on a phase of a feedback clock signal;
detecting variations in gate delays of an oscillation circuit; and
in response to detecting variations in the gate delays of the oscillation circuit, initiating a subsequent phase-lock operation.
17. The method of claim 16 , wherein detecting variations in the gate delays of the oscillation circuit includes:
counting oscillations of a clock signal output from the oscillation circuit over a predetermined time period to provide a current oscillation count; and
comparing the current oscillation count with a previous oscillation count to detect variations in the gate delays.
18. The method of claim 17 , wherein comparing the current oscillation count with the previous oscillation count to detect variations in the gate delays comprises:
subtracting a larger of the current oscillation count or the previous oscillation count from the smaller of the current oscillation count or the previous oscillation count to provide a difference value;
comparing the difference to the predetermined threshold; and
in response to the difference value exceeding the predetermined threshold, determining a variation of the phase of the clock signal.
19. The method of claim 17 , further comprising setting the predetermined time period based on a count of oscillations of the clock signal.
20. The method of claim 17 , further comprising, contemporaneously
latching the current oscillation count at a first storing circuit; and
latching the previous oscillation count at a second storing circuit.