IP Library Granted Patent US 10,192,843
Granted Patent B1
US 10,192,843 · App. 15/660,442 · Granted Jan 29, 2019

Methods of making semiconductor device modules with increased yield

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Quick Facts
Patent No.
US 10,192,843
App. No.
15/660,442
Granted
Jan 29, 2019
Kind
B1
Abstract

Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.

Claims (33)

1. A method of making a semiconductor device module, comprising:

forming holes in a sacrificial material;

placing an electrically conductive material in the holes;

removing the sacrificial material to expose posts of the electrically conductive material;

placing a stack of semiconductor dice between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack;

at least laterally encapsulating the posts and the stack of semiconductor dice in an encapsulant; and

electrically connecting bond pads of the one of the semiconductor dice to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.

2. The method of claim 1 , further comprising placing a redistribution layer in electrical communication with bond pads of the other of the semiconductor dice of the stack after at least laterally encapsulating the posts and the stack of semiconductor dice in the encapsulant.

3. The method of claim 1 , wherein placing the stack of semiconductor dice between the corresponding posts after removing the sacrificial material comprises placing the stack of semiconductor dice on a redistribution layer and electrically connecting bond pads of the other of the semiconductor dice of the stack with conductors of the redistribution layer before at least laterally encapsulating the posts and the stack of semiconductor dice in the encapsulant.

4. The method of claim 1 , further comprising removing material of at least the encapsulant to expose the bond pads before electrically connecting the bond pads to the corresponding the posts.

5. The method of claim 1 , further comprising placing a protective material over electrical connectors extending between the bond pads and the corresponding posts.

6. The method of claim 1 , further comprising encapsulating the protective material in another encapsulant.

7. The method of claim 1 , further comprising temporarily securing the sacrificial material to a support substrate before forming the holes in the sacrificial material.

8. The method of claim 7 , wherein temporarily securing the sacrificial material to the support substrate comprises placing the sacrificial material over an adhesive material comprising a metal or metal alloy material and located on the support substrate.

9. The method of claim 8 , wherein placing the electrically conductive material in the holes comprises placing the electrically conductive material in contact with at least the metal or metal alloy material.

10. The method of claim 7 , further comprising removing the support substrate after at least laterally encapsulating the posts and the stack of semiconductor dice.

11. The method of claim 1 , further comprising temporarily securing the sacrificial material to a redistribution layer before forming the holes in the sacrificial material.

12. The method of claim 11 , wherein forming the holes in the sacrificial material comprises exposing electrical conductors of the redistribution layer within the holes and wherein placing the electrically conductive material in the holes comprises electrically connecting the electrically conductive material to the electrical conductors in the holes.

13. The method of claim 12 , wherein removing the sacrificial material comprises exposing additional electrical conductors of the redistribution layer and wherein placing the stack of semiconductor dice between the corresponding posts comprises electrically connecting other bond pads of the other of the semiconductor dice of the stack to the additional electrical conductors.

14. The method of claim 11 , further comprising removing the support substrate after electrically connecting the bond pads of the one of the semiconductor dice to the corresponding posts.

15. A method of making a semiconductor device module, comprising:

forming holes in a sacrificial material;

forming posts of an electrically conductive material in the holes;

removing the sacrificial material to expose the posts of the electrically conductive material;

placing stacks of semiconductor dice between respective sets of corresponding posts after removing the sacrificial material, each stack comprising two semiconductor dice having active surfaces facing away from one another;

at least laterally encapsulating the posts and the stacks of semiconductor dice in an encapsulant;

removing material of at least the encapsulant to a predetermined thickness; and

electrically connecting bond pads of one of the semiconductor dice of each stack to the corresponding posts of the respective set after removing material of at least the encapsulant to the predetermined thickness.

16. The method of claim 15 , further comprising placing conductors of a redistribution layer in electrical communication with bond pads of the other of the semiconductor dice of at least two of the stacks after at least laterally encapsulating the posts and the stacks of semiconductor dice in the encapsulant.

17. The method of claim 15 , wherein placing the stacks of semiconductor dice between the respective sets of the corresponding posts after removing the sacrificial material comprises placing at least two stacks of semiconductor dice on a redistribution layer and electrically connecting bond pads of the other of the semiconductor dice of the at least two of the stacks with the conductors of the redistribution layer before at least laterally encapsulating the posts and the stacks of semiconductor dice in the encapsulant.

18. The method of claim 15 , further comprising temporarily securing the sacrificial material to a support substrate before forming the holes in the sacrificial material.

19. The method of claim 15 , further comprising temporarily securing the sacrificial material to a redistribution layer before forming the holes in the sacrificial material.

20. The method of claim 19 , wherein forming the holes in the sacrificial material comprises exposing electrical conductors of the redistribution layer within the holes and wherein forming posts of the electrically conductive material in the holes comprises electrically connecting the posts to the electrical conductors.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: PACHAMUTHU, ASHOK; YOO, CHAN H.; HO, SZU-YING; KAEDING, JOHN F.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043349/0629 →