Reference voltage generator with adaptive voltage and integrated circuit chip
There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.
1. A reference voltage generator, comprising: a steady current source configured to provide a steady current; a PMOS transistor, a source electrode of the PMOS transistor being configured to receive the steady current, and the PMOS transistor having a first gate-source voltage; and an NMOS transistor, a drain electrode of the NMOS transistor being electrically coupled to a drain electrode of the PMOS transistor, and the NMOS transistor having a second gate-source voltage, wherein a reference voltage provided by the reference voltage generator is determined by the first gate-source voltage and the second gate-source voltage, the drain electrode of the NMOS transistor is directly connected to the drain electrode of the PMOS transistor at a node, and gate electrodes of the PMOS transistor and the NMOS transistor are connected to the node such that the drain and gate electrodes of the PMOS transistor and the drain and gate electrodes of the NMOS transistor are connected together, wherein an additional PMOS transistor and at least one another NMOS transistor are further coupled between the drain electrodes of the NMOS transistor and the PMOS transistor.
2. The reference voltage generator as claimed in claim 1 , wherein a plurality of other PMOS transistors and a plurality of other NMOS transistors are further coupled between the drain electrodes of the NMOS transistor and the PMOS transistor, and a number of the coupled other PMOS transistors and other NMOS transistors are adjustable.
3. The reference voltage generator as claimed in claim 1 , wherein the steady current provided by the steady current source is adjustable.
4. A reference voltage generator, comprising: a PMOS transistor having a first gate-source voltage; an NMOS transistor, a drain electrode of the NMOS transistor being electrically coupled to a drain electrode of the PMOS transistor, and the NMOS transistor having a second gate-source voltage; and a steady current source configured to provide a steady current flowing out from a source electrode of the NMOS transistor, wherein a reference voltage provided by the reference voltage generator is determined by the first gate-source voltage and the second gate-source voltage, the drain electrode of the NMOS transistor is directly connected to the drain electrode of the PMOS transistor at a node, and gate electrodes of the PMOS transistor and the NMOS transistor are connected to the node such that the drain and gate electrodes of the PMQS transistor and the drain and gate electrodes of the NMQS transistor are connected together, wherein at least one another an additional PMOS transistor and at least one another NMOS transistor are further coupled between the drain electrodes of the NMOS transistor and the PMOS transistor.
5. The reference voltage generator as claimed in claim 4 , wherein a plurality of other PMOS transistors and a plurality of other NMOS transistors are further coupled between the drain electrodes of the NMOS transistor and the PMOS transistor, and a number of the coupled other PMOS transistors and other NMOS transistors are adjustable.
6. The reference voltage generator as claimed in claim 4 , wherein the steady current provided by the steady current source is adjustable.
7. An integrated circuit chip, wherein
a reference voltage generator comprising a steady current source, at least one PMOS transistor and at least one NMOS transistor cascadely coupled to one another, wherein the at least one PMOS transistor has a first gate-source voltage, the at least one NMOS transistor has a second gate-source voltage, and the reference voltage generator is configured to provide a reference voltage which is determined by the first gate-source voltage and the second gate-source voltage;
a regulator configured to receive the reference voltage and generate a regulated voltage; and
a high-frequency circuit configured to take the regulated voltage as a power source voltage, wherein the power source voltage is an adaptive voltage varying with temperature and manufacturing processes.
8. The integrated circuit chip as claimed in claim 7 , wherein the steady current source is configured to provide a steady current flowing into a source electrode of the at least one PMOS transistor.
9. The integrated circuit chip as claimed in claim 7 , wherein the steady current source is configured to provide a steady current flowing out from a source electrode of the at least one NMOS transistor.
10. The integrated circuit chip as claimed in claim 8 , wherein the steady current provided by the steady current source is adjustable.
11. The integrated circuit chip as claimed in claim 7 , wherein the reference voltage generator comprises the steady current source, a plurality of PMOS transistors and a plurality of NMOS transistors cascadely coupled to one another, and a number of the coupled PMOS transistors and the NMOS transistors are adjustable.
12. The integrated circuit chip as claimed in claim 7 , wherein the high-frequency circuit is a divider.