Apparatuses and methods for generating a voltage in a memory
View Patent ↗Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
1. An apparatus, comprising:
a pull-up circuit configured to be coupled to a power supply and coupled to an output node at which an output voltage is provided;
a capacitance coupled to the output node and to a gate node of the pull-up circuit;
a pull-down circuit configured to be coupled to a reference voltage and coupled to the output node;
an input circuit coupled to the output node and to a gate node of the pull-down circuit, the input circuit configured to receive an input voltage;
a first transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the first transistor configured to receive a first bias signal; and
a second transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the second transistor configured to receive a second bias signal.
2. The apparatus of claim 1 , further comprising a bias circuit configured to provide the first bias signal, wherein the bias circuit comprises:
a first load circuit configured to have a first threshold voltage matched to a threshold voltage of the pull-down circuit;
a second load circuit configured to have a second threshold voltage matched to a threshold voltage of the first transistor, and
a current source circuit, wherein the current source circuit, the first load circuit, and the second load circuit are coupled in series.
3. The apparatus of claim 2 wherein the first load circuit comprises a first load coupled transistor and wherein the second load circuit comprises a second load coupled transistor.
4. The apparatus of claim 1 , further comprising a bias circuit configured to provide the second bias signal, wherein the bias circuit comprises:
a first load circuit configured to have a first threshold voltage matched to a threshold voltage of the pull-up circuit;
a second load circuit configured to have a second threshold voltage matched to a threshold voltage of the second transistor; and
a current source circuit, wherein the current source circuit, the first load circuit, and the second load circuit are coupled in series.
5. The apparatus of claim 4 wherein a size of the pull-up circuit is scaled relative to a size of the first load circuit.
6. The apparatus of claim 1 wherein the reference voltage comprises ground.
7. The apparatus of claim 1 , further comprising:
a first current source circuit configured to be coupled to a power supply and coupled to the gate node of the pull-up circuit; and
a second current source circuit configured to be coupled to the reference voltage and coupled to the gate node of the pull-down circuit.
8. The apparatus of claim 7 wherein the first current source circuit is configured to provide a first current and the second current source circuit is configured to provide a second current, wherein the second current is greater than the first current.