IP Library › Granted Patent US 10,425,189
Granted Patent B2
US 10,425,189 · App. 15/663,581 · Granted Sep 24, 2019

Method for processing data block in LDPC encoder

Inventors: Bonghoe Kim (Seoul, KR); Byounghoon Kim (Seoul, KR); Kwangseok Noh (Seoul, KR); Joonkui Ahn (Seoul, KR)
Assignee: LG ELECTRONICS INC.
H04L1/0057H03M13/091H03M13/116H03M13/1174H03M13/2906H03M13/353H03M13/616H03M13/618H03M13/6356H03M13/6362H03M13/6508H03M13/6516H03M13/6525H04L1/0068H03M13/09H04L1/0061
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Quick Facts
Patent No.
US 10,425,189
App. No.
15/663,581
Granted
Sep 24, 2019
Kind
B2
Abstract

A method for communication device processing a data block in a low-density parity-check (LDPC) encoder includes the steps of, if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation, and performing encoding in a unit of a code block on code blocks according to the code block segmentation. In this case, the code block segmentation may be performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder.

Claims (33)

1. A method for a communication device processing a data block based on a low-density parity-check (LDPC) encoder, the method comprising:

receiving, from a base station (BS), information related to a code block segmentation for the data block;

generating, by the LDPC encoder, code blocks based on the information related to the code block segmentation,

wherein a size of a payload for the data block is equal to or greater than a threshold value;

performing, by the LDPC encoder, error correction based on encoding for each of the code blocks; and

transmitting, to the BS, the code blocks,

wherein the code block segmentation is based on a payload size supported by a parity check matrix (H), and

wherein the parity check matrix (H) is related to a coding rate of the LDPC encoder.

2. The method of claim 1 , wherein the code block segmentation is performed to minimize a number of the code blocks.

3. The method of claim 1 , wherein the code block segmentation is based on one of a plurality of payload sizes supported by the parity check matrix (H).

4. The method of claim 1 , further comprising:

performing rate matching or shortening, when a size of an encoded bit based on the encoding is not a size defined by the parity check matrix (H) related to the coding rate of the LDPC encoder.

5. The method of claim 4 , wherein the rate matching comprises puncturing or repetition.

6. The method of claim 1 , further comprising:

attaching a cyclic redundancy check CRC to each of the code blocks after the code block segmentation.

7. The method of claim 1 , wherein the payload is segmented into different payload sizes supported by the parity check matrix (H) related to the coding rate of the LDPC encoder.

8. A communication device for processing a data block, the communication device comprising:

a radio frequency (RF) unit to transmit and receive information;

a low-density parity-check (LDPC) encoder; and

a processor connected to the RF unit and the LDPC encoder, and configured to:

control the RF unit to receive, from a base station (BS), information related to a code block segmentation for the data block;

control the LDPC encoder to generate code blocks based on the information related to the code block segmentation,

wherein a size of a payload for the data block is equal to or greater than a threshold value;

control the LDPC encoder to perform error correction based on encoding for each of the code blocks; and

control the RF unit to transmit, to the BS, the code blocks,

wherein the code block segmentation is based on a payload size supported by a parity check matrix (H), and

wherein the parity check matrix (H) is related to a coding rate of the LDPC encoder.

9. The communication device of claim 8 , wherein the code block segmentation is performed to minimize a number of the code blocks.

10. The communication device of claim 8 , wherein the code block segmentation is based on one of a plurality of payload sizes supported by the parity check matrix (H).

11. The communication device of claim 8 , wherein the processor is further configured to control the LDPC encoder to perform rate matching or shortening, when a size of an encoded bit based on the encoding is not a size defined by the parity check matrix (H) related to the coding rate of the LDPC encoder.

12. The communication device of claim 11 , wherein the rate matching comprises puncturing or repetition.

13. The communication device of claim 8 , wherein the processor is configured to attach a cyclic redundancy check CRC to each of the code blocks after the code block segmentation.

14. The communication device of claim 8 , wherein the payload is segmented into different payload sizes supported by the parity check matrix (H) related to the coding rate of the LDPC encoder.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KIM, BONGHOE; KIM, BYOUNGHOON; NOH, KWANGSEOK; AHN, JOONKUI
To: LG ELECTRONICS INC.
Reel/Frame 043392/0615 →
Continuity (2)
Provisional Application 62368198 · Jul 29, 2016
Related Publication 20180034585A1 · Feb 1, 2018