Memory arrays
View Patent ↗Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
1. A memory array, comprising:
a series of bitlines, each of the bitlines having a first comparative bitline component and a second comparative bitline component; the bitlines defining columns of the memory array;
memory cells along the columns of the memory array;
capacitive units along the columns of the memory array and interspersed amongst the memory cells;
wherein the capacitive units are identically configured as the memory cells and differ from the memory cells in a method of operation; and
wherein the memory cells each include two transistors and a capacitor.
2. A memory array, comprising;
a series of bitlines, each of the bitlines having a first comparative bitline component and a second comparative bitline component; the bitlines defining columns of the memory array;
memory cells along the columns of the memory array;
capacitative units along the columns of the memory array and interspersed amongst the memory cells;
wherein the capacitative units are identically configured as the memory cells and differ from the memory cells in a method of operation; and
wherein the memory cells each include two transistors and two capacitors.
3. A memory array, comprising:
a series of bitlines, each of the bitlines having a first comparative bitline component and a second comparative bitline component; the bitlines defining columns of the memory array;
memory cells along the columns of the memory array;
capacitive units along the columns of the memory array and interspersed amongst the memory cells;
wherein the capacitative units are identically configured as the memory cells and differ from the memory cells in a method of operation; and
wherein the difference in the method of operation is that data is not stored on the capacitive units, and instead the capacitive units are maintained in an “on” state during READ operations associated with memory cells of the array.
4. The memory array of claim 3 wherein the capacitive units are also maintained in the “on” state during WRITE operations associated with memory cells of the array.
5. The memory array of claim 3 wherein the capacitive units are not maintained in the “on” state during WRITE operations associated with memory cells of the array.
6. A memory array comprising:
a series of bitlines, each of the bitlines having a first comparative bitline component and a second comparative bitline component; the bitlines defining columns of the memory array;
memory cells along the columns of the memory array; individual memory cells comprising first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors; the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes; the first and second transistors being coupled to a common wordline; and
capacitive units along the columns of the memory array; individual capacitive units being configured identically to the individual memory cells but not being utilized for data storage during operation of the memory array, an individual capacitive unit along an individual column being maintained in an “on” state when said individual column is utilized in a READ operation.
7. The memory array of claim 6 wherein said individual capacitive unit is not maintained in the “on” state when said individual column is utilized in a WRITE operation.
8. The memory array of claim 6 wherein said individual capacitive unit is maintained in the “on” state when said individual column is utilized in a WRITE operation.
9. The memory array of claim 6 wherein said individual capacitive unit is along a row of capacitive units.
10. The memory array of claim 9 wherein said individual capacitive unit is also maintained in the “on” state when any column crossing said row is utilized in a READ operation.
11. The memory array of claim 6 wherein the first transistor, second transistor and capacitor of the individual memory cells and the individual capacitive units are all in a common vertical plane as one another.
12. The memory array of claim 6 wherein the columns of the memory array have two or more of the capacitive units.
13. A memory array comprising:
a series of bitlines, each of the bitlines having a first comparative bitline component and a second comparative bitline component; the bitlines defining columns of the memory array;
memory cells along the columns of the memory array; individual memory cells comprising first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors; the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes; the first and second transistors being coupled to a common wordline; and
capacitive units along the columns of the memory array; individual capacitive units being configured identically to the individual memory cells but not being utilized for data storage during operation of the memory array, an individual capacitive unit being maintained in an “on” state whenever power is provided to the memory array.
14. The memory array of claim 13 wherein said individual capacitive unit is along a row of capacitive units.
15. The memory array of claim 13 wherein the first transistor, second transistor and capacitor of the individual memory cells and the individual capacitive units are all in a common vertical plane as one another.
16. The memory array of claim 13 wherein the columns of the memory array have two or more of the capacitive units.
17. An apparatus comprising a semiconductor base, a memory array, and an insulating film intervening between the semiconductor base and the memory array, the memory array including a plurality of memory cells, a pair of bitlines, and at least one capacitive unit, and each of the plurality of memory cells being provided between the pair of bitlines;
wherein each of the memory cells comprises a first transistor and a first capacitor, the first transistor and the first capacitor being vertically disposed between the pair of bitlines;
wherein the at least one capacitive unit is disposed between the pair of bitlines and activated at least when one of the memory cells is accessed to read data therefrom; and
wherein the at least one capacitive unit is configured identically to the memory cells.
18. The apparatus of claim 17 , wherein each of the memory cells further comprises a second transistor, and wherein the first transistor, the first capacitor and the second transistor are vertically disposed between the pair of bitlines with the first and second transistors sandwiching the capacitor therebetween.
19. The apparatus of claim 18 , wherein the at least one capacitive unit comprises a third transistor, a second capacitor and a fourth transistor that are vertically disposed between the pair of bitlines, and wherein the each of the third and fourth transistors are turned ON at least when one of the memory cells is accessed to read data therefrom.
20. The apparatus of claim 17 , wherein each of the plurality of memory cells further comprises a first semiconductor pillar, wherein the first semiconductor pillar includes first, second and third portions serving as one of a source and a drain of the first transistor, a channel of the first transistor and the other of the source and the drain of the first transistor, respectively, and wherein one of the first and third portions of the first semiconductor pillar is electrically connected with a first node of the first capacitor.
21. The apparatus of claim 20 , wherein the first capacitor includes a second node and a dielectric material between the first and second nodes, and wherein the first semiconductor pillar, the first node, the dielectric material and the second node are vertically disposed.
22. The apparatus of claim 20 , wherein each of the plurality of memory cells further comprises a second transistor and a second semiconductor pillar, wherein the second semiconductor pillar includes fourth, fifth and sixth portions serving as one of a source and a drain of the second transistor, a channel of the second transistor and the other of the source and the drain of the second transistor, respectively, and wherein one of the fourth and sixth portions of the second semiconductor pillar is electrically connected with a second node of the first capacitor.
23. The apparatus of claim 22 , wherein the first and second transistors and the first capacitor are connected in series between the pair of bitlines.