Apparatuses and methods for bi-directional access of cross-point arrays
View Patent ↗The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
1. A method, comprising:
applying a first bias across a memory cell during a selection phase of an access operation, the first bias having a first polarity;
removing the first bias, wherein a current flowing through the memory cell falls below a minimum hold current based at least in part on the removing the first bias; and
applying a second bias across the memory cell during an access phase of the access operation, the second bias lower in magnitude than the first bias and having a second polarity.
2. The method of claim 1 , wherein the access operation sets a logical value of the memory cell, the first polarity being the same as the second polarity.
3. The method of claim 1 , wherein the access operation re-sets a logical value of the memory cell, the first polarity being different from the second polarity.
4. The method of claim 3 , wherein applying the first bias causes a first snap-back discharge current to flow through the memory cell in a first direction, and wherein applying the second bias causes a second snap-back discharge current lower in magnitude than the first snap-back discharge current to flow through the memory cell in a second direction different than the first direction.
5. The method of claim 1 , wherein applying the first bias comprises:
applying a first voltage across a column access line of the memory cell and applying a second voltage, lower in magnitude than the first voltage, across a row access line of the memory cell.
6. The method of claim 5 , wherein applying the second bias comprises:
applying a third voltage across the column access line of the memory cell, the third voltage having a first magnitude between the first voltage and the second voltage; and
applying a fourth voltage across the row access line of the memory cell, the fourth voltage having a second magnitude between the second voltage and the third voltage.
7. The method of claim 5 , wherein applying the second bias comprises:
applying a third voltage across the column access line of the memory cell, the third voltage having a first magnitude between the first voltage and the second voltage; and
applying a fourth voltage across the row access line of the memory cell, the fourth voltage having a second magnitude between the first voltage and the third voltage.
8. The method of claim 1 , wherein the second bias is applied within less than about 5 microseconds after removing the first bias.
9. An apparatus, comprising:
a memory cell; and
a memory controller configured to:
apply a first bias across the memory cell during a selection phase of an access operation, the first bias having a first polarity;
remove the first bias, wherein a current flowing through the memory cell falls below a minimum hold current based at least in part on the removal of the first bias; and
apply a second bias across the memory cell during an access phase of the access operation, the second bias lower in magnitude than the first bias and having a second polarity.
10. The apparatus of claim 9 , wherein the memory controller is configured to apply the first bias by:
generating a first voltage differential across a first access line of the memory cell; and
generating a second voltage differential, lower in magnitude than the first voltage differential, across a second access line of the memory cell, the second access line orthogonal to the first access line.
11. The apparatus of claim 10 , wherein the memory controller is configured to apply the second bias by:
generating a third voltage differential across the first access line of the memory cell, the third voltage differential having a first magnitude between the first voltage differential and the second voltage differential; and
generating a fourth voltage differential across the second access line of the memory cell, the fourth voltage differential having a second magnitude between the second voltage differential and the third voltage differential.
12. The apparatus of claim 10 , wherein the memory controller is configured to apply the second bias by:
generating a third voltage drop across the first access line of the memory cell, the third voltage drop having a first magnitude between the first voltage differential and the second voltage differential; and
generating a fourth voltage drop across the second access line of the memory cell, the fourth voltage drop having a second magnitude between the first voltage differential and the third voltage drop.
13. The apparatus of claim 9 , wherein the memory controller is configured to apply the second bias within a predetermined duration after the removal of the first bias.
14. An apparatus, comprising:
a memory cell having a first section and a second section;
a first voltage source electrically coupled with the first section of the memory cell via a first circuit path;
a second voltage source electrically coupled with the second section of the memory cell via a second circuit path; and
a third voltage source electrically coupled with the first section of the memory cell via a third circuit path,
wherein the first voltage source and the second voltage source are configured to create a first voltage differential having a first polarity across the memory cell during a first phase of an access operation.
15. The apparatus of claim 14 , wherein the first voltage source comprises a column selection voltage source or a mid-bias column voltage source, and wherein the second voltage source is a reference voltage source.
16. The apparatus of claim 14 , wherein the third voltage source and the second voltage source are configured to create a second voltage differential across the memory cell during a second phase of the access operation, the second voltage differential lower in magnitude than the first voltage differential and having the first polarity.
17. The apparatus of claim 16 , wherein the third voltage source comprises a mid-bias column voltage source or a reference voltage source.
18. The apparatus of claim 16 , wherein the access operation sets a logic value of the memory cell.
19. The apparatus of claim 14 , wherein the third voltage source and the second voltage source create a second voltage differential across the memory cell during a second phase of the access operation, the second voltage differential lower in magnitude than the first voltage differential and having a second polarity different from the first polarity.
20. The apparatus of claim 19 , wherein the third voltage source comprises a reference voltage source or a row selection voltage source.