Methods of determining host clock frequency for run time optimization of memory and memory devices employing the same
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.
1. A memory device comprising:
one or more memories;
a connector operably coupled to the one or more memories and configured to receive signals from a connected host, the signals including a first reference clock signal; and
circuitry configured to determine a frequency of the first reference clock signal,
wherein the circuitry configured to determine a frequency of the first reference clock signal includes:
circuitry configured to generate a second reference clock signal; and
circuitry configured to compare the first and second reference clock signals to determine the frequency of the first reference clock signal.
2. The memory device of claim 1 , wherein the circuitry configured to compare the first and second reference clock signals includes:
circuitry configured to count edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
3. The memory device of claim 1 , further comprising:
circuitry configured to store the determined frequency.
4. The memory device of claim 1 , further comprising:
circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.
5. The memory device of claim 1 , wherein the one or more operating characteristics include one or more of path delays for DLLs, voltage, and timing.
6. The memory device of claim 1 , wherein the signals from the connected host do not include an indication of the frequency of the first reference clock signal.
7. The memory device of claim 1 , wherein the one or more memories are DRAM memories.
8. The memory device of claim 1 , wherein the connector is an edge connector.
9. The memory device of claim 1 , wherein the memory device is a dual in-line memory module (DIMM).
10. The memory device of claim 1 , wherein the one or more memories include at least one non-volatile memory.
11. The memory device of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).
12. A memory module, comprising:
a plurality of volatile memories;
a connector operably coupled to the one or more memories and configured to receive signals from a connected host, the signals including a first reference clock signal;
circuitry configured to determine a frequency of the first reference clock signal; and
circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal,
wherein the circuitry configured to determine a frequency of the first reference clock signal includes:
circuitry configured to generate a second reference clock signal; and
circuitry configured to compare the first and second reference clock signals to determine the frequency of the first reference clock signal.
13. The memory module of claim 12 , wherein the circuitry configured to compare the first and second reference clock signals includes:
circuitry configured to count edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
14. The memory module of claim 12 , further comprising:
circuitry configured to store the determined frequency.
15. A method of operating a memory device, comprising:
receiving, from a connected host, a first reference clock signal;
comparing the first reference clock signal to a second reference clock signal of a predetermined second frequency to determine a first frequency of the first reference clock signal; and
adjusting one or more characteristics of the memory device in response to the determined first frequency of the first reference clock signal.
16. The method of claim 15 , wherein the comparing the first reference clock signal to the second reference clock signal to includes:
counting edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
17. The method of claim 15 , wherein the one or more operating characteristics include one or more of path delays for DLLs, voltage, and timing.
18. The method of claim 15 , wherein the connected host does not provide the memory device with an indication of the frequency of the first reference clock signal.