IP Library Granted Patent US 10,299,389
Granted Patent B2
US 10,299,389 · App. 15/666,444 · Granted May 21, 2019

Rigid-flexible circuit interconnects

Inventor: Wei Shi (San Jose, CA)
Assignee: FINISAR CORPORATION
H05K3/363H05K3/36H01L23/49822H01L23/49833H01L23/49838H01L23/49855H01L2924/0002H05K2201/0367H05K2201/099H05K2201/09445H05K2201/09781H05K2201/2036
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Quick Facts
Patent No.
US 10,299,389
App. No.
15/666,444
Granted
May 21, 2019
Kind
B2
Abstract

In an example embodiment, a circuit interconnect includes a first printed circuit board (PCB), a second PCB, a spacer, and an electrically conductive solder joint. The first PCB includes a first electrically conductive pad. The second PCB includes a second electrically conductive pad. The spacer is configured to position the first PCB relative to the second PCB such that a space remains between the first PCB and the second PCB after the first electrically conductive pad and the second electrically conductive pad are conductively connected in a soldering process. The electrically conductive solder joint conductively connects the first electrically conductive pad and the second electrically conductive pad.

Claims (14)

1. A circuit interconnect comprising:

a first printed circuit board (PCB) including a first electrically conductive pad;

a second PCB including a second electrically conductive pad;

a spacer configured to position the first PCB relative to the second PCB such that a space is defined between the first PCB and the second PCB after the first electrically conductive pad and the second electrically conductive pad are conductively connected in a soldering process, the spacer consisting of:

a first PCB spacer consisting of a first electrically conductive plate located on the first PCB and a first dielectric layer located on the first electrically conductive plate; and

a second PCB spacer adjacent to the first PCB spacer, the second PCB spacer consisting of a second electrically conductive plate located on the second PCB and a second dielectric layer located on the second electrically conductive plate.

2. The circuit interconnect of claim 1 , further comprising an electrically conductive solder joint mechanically connecting the first electrically conductive pad and the second electrically conductive pad.

3. The circuit interconnect of claim 1 , further comprising a dielectric support located at least in part within the space defined by the first PCB and the second PCB.

4. The circuit interconnect of claim 1 , wherein the first PCB includes a rigid PCB and the second PCB includes a flexible PCB.

5. The circuit interconnect of claim 1 , wherein the first electrically conductive pad is a fine-pitch pad and the second electrically conductive pad is a fine-pitch pad.

6. The circuit interconnect of claim 1 , wherein the first electrically conductive pad has a diameter equal to or less than 0.28 millimeters (mm) and the second electrically conductive pad has a diameter equal to or less than 0.28 mm.

7. The circuit interconnect of claim 1 , wherein the first PCB further includes a third electrically conductive pad, and a distance from a center of the first electrically conductive pad and a center of the third electrically conductive pad is equal to or less than 0.7 millimeters.

8. The circuit interconnect of claim 1 , wherein a height of the first PCB spacer is substantially equivalent to a height of the second PCB spacer.

9. The circuit interconnect of claim 1 , wherein an aggregate height of the first PCB spacer and the second PCB is substantially equivalent to a height of the space that is defined between the first PCB and the second PCB after the first electrically conductive pad and the second electrically conductive pad are conductively connected.

Assignments (5)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2019
From: SHI, WEI
To: FINISAR CORPORATION
Reel/Frame 048620/0458 →
Continuity (3)
Continuation 14289249 · May 28, 2014
Provisional Application 61828312 · May 29, 2013
Related Publication 20180054898A1 · Feb 22, 2018