Nonvolatile semiconductor memory device and manufacturing method thereof
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
1. A nonvolatile semiconductor memory device comprising:
a first structure having a first semiconductor layer, first electrode layers, first insulating layers and a first memory portion, the first semiconductor layer extending in a first direction, the first electrode layers and the first insulating layers alternately stacked in the first direction, the first memory portion provided between the first semiconductor layer and one of the first electrode layers, and the first electrode layers including a first contact region formed in a shape of stairs; and
a second structure having a second semiconductor layer, second electrode layers, second insulating layers and a second memory portion, the second semiconductor layer extending in the first direction, the second electrode layers and the second insulating layers alternately stacked in the first direction, the second memory portion provided between the second semiconductor layer and one of the second electrode layers, and the second electrode layers including a second contact region formed in a shape of stairs, and
wherein the first structure and the second structure are arranged in a second direction crossing the first direction, and the first contact region and the second contact region are not arranged between the first structure and the second structure.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein
the first contact region is arranged on a side opposite to a region between the first structure and the second structure in the second direction, and
the second contact region is arranged on the side opposite to the region between the first structure and the second structure in the second direction.
3. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a first insulation film formed around the first semiconductor layer;
a charge storage layer formed around the first insulation film;
a second insulation film formed around the charge storage layer; and
a plurality of third insulation films formed around the second insulation film, the third insulation films being formed between the first electrode layers, respectively.
4. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a plurality of plugs, each of the plugs being connected electrically to an upper surface of each of the first electrode layers in the first contact region formed in the shape of stairs.
5. The nonvolatile semiconductor memory device according to claim 4 , wherein each of the first electrode layers is connected to a word line driver via each of the plugs.
6. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a third structure having a third semiconductor layer, third electrode layers, third insulating layers and a third memory portion, the third semiconductor layer extending in the first direction, the third electrode layers and the third insulating layers alternately stacked in the first direction, the third memory portion provided between the third semiconductor layer and one of the third electrode layers, and the third electrode layers including a third contact region formed in a shape of stairs; and
a fourth structure having a fourth semiconductor layer, a fourth electrode layers, a fourth insulating layers and a fourth memory portion, the fourth semiconductor layer extending in the first direction, the fourth electrode layers and the fourth insulating layers alternately stacked in the first direction, the fourth memory portion provided between the fourth semiconductor layer and one of the fourth electrode layers, and the fourth electrode layers including a fourth contact region formed in a shape of stairs, and
wherein the third structure and the fourth structure are arranged in the second direction, and the third contact region and the fourth contact region are not arranged between the third structure and the fourth structure.
7. The nonvolatile semiconductor memory device according to claim 6 , wherein
the third contact region is arranged on a side opposite to a region between the third structure and the fourth structure in the second direction, and
the fourth contact region is arranged on the side opposite to the region between the third structure and the fourth structure in the second direction.
8. The nonvolatile semiconductor memory device according to claim 6 , wherein
the third structure and the first structure are arranged in a third direction crossing the first direction and the second direction, the fourth structure and the second structure are arranged in the third direction,
the first contact region, the second contact region, the third contact region and the fourth contact region are not arranged between the third structure and the fourth structure,
the first contact region, the second contact region, the third contact region and the fourth contact region are not arranged between the first structure and the third structure, and
the first contact region, the second contact region, the third contact region and the fourth contact region are not arranged between the second structure and the fourth structure.
9. The nonvolatile semiconductor memory device according to claim 6 , wherein
the third contact region is provided at an edge region of the third electrode layers in the third direction and on a side opposite to a region between the third structure and the fourth structure, and
the fourth contact region is provided at an edge region of the fourth electrode layers in the third direction and on the side opposite to the region between the third structure and the fourth structure.
10. The nonvolatile semiconductor memory device according to claim 9 , wherein
the third structure is arranged in the third direction for the first structure, and the fourth structure is arranged in the third direction for the second structure.
11. The nonvolatile semiconductor memory device according to claim 6 , wherein
the second structure is arranged adjacent to the third structure in the second direction, and the second contact region is arranged to face the third contact region in the second direction.
12. The nonvolatile semiconductor memory device according to claim 11 , wherein
the third contact region is arranged on a side opposite to a region between the third structure and the fourth structure in the second direction, and
the fourth contact region is arranged on the side opposite to the region between the third structure and the fourth structure.
13. The nonvolatile semiconductor memory device according to claim 6 , wherein
the third structure is arranged in the second direction, and the fourth structure is arranged in the second direction,
the third contact region and the fourth contact region are not arranged between the third structure and the fourth structure.
14. The nonvolatile semiconductor memory device according to claim 1 , further comprising a third semiconductor layer, a third memory portion, a fourth semiconductor layer and a fourth memory portion:
the third memory portion is provided between the third semiconductor layer and the first electrode layer shared with the first memory portion, the third memory portion is adjacent to the first memory portion in the second direction, and
the fourth memory portion is provided between the fourth semiconductor layer and the first electrode layer shared with the first memory portion, the fourth memory portion is adjacent to the first memory portion in the third direction.