Sense amplifier constructions
A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
1. A sense amplifier construction comprising:
a first n-type transistor and a second n-type transistor extending elevationally outward relative to be vertically offset from the first n-type transistor, the first transistor comprising a first semiconductor material pillar extending along a first gate and comprising a first channel region elevationally between first transistor top and bottom n-type source/drain regions, the second transistor comprising a second semiconductor material pillar extending along a second gate and comprising a second channel region elevationally between second transistor top and bottom n-type source/drain regions;
a third p-type transistor and a fourth p-type transistor extending elevationally outward relative to the third p-type transistor, the third transistor comprising a third semiconductor material pillar extending along a third gate and comprising a third channel region elevationally between third transistor top and bottom p-type source/drain regions, the fourth transistor comprising a fourth semiconductor material pillar extending along a fourth gate and comprising a fourth channel region elevationally between fourth transistor top and bottom p-type source/drain regions;
a lower voltage activation line electrically coupled to each of the top source/drain region of the first transistor and the bottom source/drain region of the second transistor; and
a higher voltage activation line electrically coupled to each of the top source/drain region of the third transistor and the bottom source/drain region of the fourth transistor.
2. The sense amplifier construction of claim 1 wherein the second semiconductor material pillar is vertically offset directly above the first semiconductor material pillar.
3. The sense amplifier construction of claim 1 wherein the lower voltage activation line is elevationally between the top source/drain region of the first transistor and the bottom source/drain region of the second transistor.
4. The sense amplifier construction of claim 1 wherein,
the second semiconductor material pillar is vertically offset directly above the first semiconductor material pillar;
a top of the first semiconductor material pillar is directly against a bottom of the second semiconductor material pillar and the top source/drain region of the first transistor and the bottom source/drain region of the second transistor comprise a common same shared source/drain region of the first and second transistors; and
the lower voltage activation line is directly against a side surface of the shared source/drain region of the first and second transistors.
5. The sense amplifier construction of claim 1 wherein the fourth semiconductor material pillar is vertically offset directly above the first semiconductor material pillar.
6. The sense amplifier construction of claim 1 wherein the higher voltage activation line is elevationally between the top source/drain region of the third transistor and the bottom source/drain region of the fourth transistor.
7. The sense amplifier construction of claim 6 wherein the top source/drain region of the third transistor is directly against a bottom surface of the higher voltage activation line and the bottom source/drain region of the fourth transistor is directly against a top surface of the higher voltage activation line.
8. The sense amplifier construction of claim 1 wherein,
the fourth semiconductor material pillar is vertically offset directly above the third semiconductor material pillar;
a top of the third semiconductor material pillar is directly against a bottom of the fourth semiconductor material pillar and the top source/drain region of the third transistor and the bottom source/drain region of the fourth transistor comprise a common same shared source/drain region of the third and fourth transistors; and
the higher voltage activation line is directly against a side surface of the shared source/drain region of the third and fourth transistors.
9. The sense amplifier construction of claim 1 wherein the third semiconductor material pillar is spaced aside the first semiconductor material pillar.
10. The sense amplifier construction of claim 1 wherein the fourth semiconductor material pillar is spaced aside the second semiconductor material pillar.
11. The sense amplifier construction of claim 1 wherein the first, second, third, and fourth semiconductor material pillars extend vertically or within 10° of vertical.
12. The sense amplifier construction of claim 11 wherein the first, second, third, and fourth semiconductor material pillars extend vertically; the first and third pillars being spaced aside and elevationally coincident relative one another; the third and fourth pillars being spaced aside and elevationally coincident relative one another.
13. A latch-based sense amplifier construction comprising:
a first n-type transistor and a second n-type transistor vertically offset above the first n-type transistor;
a lower voltage activation line electrically coupled to n-type source/drain regions of the first and second n-type transistors that are elevationally between respective gates of the first and second n-type transistors;
a third p-type transistor aside the first n-type transistor, a fourth p-type transistor vertically offset above the third p-type transistor and aside the second n-type transistor;
a higher voltage activation line electrically coupled to p-type source/drain regions of the third and fourth p-type transistors that are elevationally between respective gates of the third and fourth p-type transistors;
a first lower conductor directly electrically coupling gates of the first and third transistors together;
a second upper conductor directly electrically coupling top source/drain regions of the second and fourth transistors together, the first conductor being directly electrically coupled to the second conductor;
a third lower conductor directly electrically coupling bottom source/drain regions of the first and third transistors together; and
a fourth upper conductor directly electrically coupling gates of the second and fourth transistors together, the third conductor being directly electrically coupled to the fourth conductor.
14. The latch-based sense amplifier construction of claim 13 wherein the first, second, third, and fourth transistors are each vertical or within 10° of vertical.
15. The latch-based sense amplifier construction of claim 13 wherein the first lower conductor is vertically offset above the third lower conductor.
16. The latch-based sense amplifier construction of claim 13 wherein the second upper conductor is vertically offset above the fourth upper conductor.
17. The latch-based sense amplifier construction of claim 13 wherein the third lower conductor is directly electrically coupled to the fourth upper conductor at least in part by a pillar comprising conductively-doped semiconductor material.
18. The latch-based sense amplifier construction of claim 13 wherein the first, second, third, and fourth conductors comprise horizontally-extending metal material; the first lower conductor being directly electrically coupled to the second upper conductor at least in part by a vertically-extending pillar comprising conductively-doped semiconductor material; and the third lower conductor being directly electrically coupled to the fourth upper conductor at least in part by another vertically-extending pillar comprising conductively-doped semiconductor material.