Capacitively-coupled field-plate structures for semiconductor devices
Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate;
a field-plate dielectric disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact;
one or more coupling capacitors; and
one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact,
wherein at least one of the capacitively-coupled field plates is disposed on the field-plate dielectric, and
wherein each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through a corresponding coupling capacitors, the corresponding coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the corresponding capacitively-coupled field plate.
2. The semiconductor device of claim 1 ,
wherein the semiconductor device comprises two or more capacitively-coupled field plates,
wherein a first capacitively-coupled field plate is positioned closer to the first ohmic contact than a second capacitively-coupled field plate, and
wherein a first coupling capacitor connected to the first capacitively-coupled field plate has a larger capacitance than a second coupling capacitor connected to the second capacitively-coupled field plate.
3. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises one or more semiconductor layers, each semiconductor layer comprising one or more materials selected from the group consisting of Si, SiC, Ge, ZnO, ZnO 2 , Ga 2 O 3 , InAl y Ga z As (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), GaN, AlGaN, and In x Al y Ga z N (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1).
4. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a material selected from the group consisting of Group IV, Group III-V, Group II-VI, and Group III-Nitride (III-N) semiconductor materials.
5. The semiconductor device of claim 1 , wherein the one or more capacitively-coupled field plates do not overlap with one another over the semiconductor substrate.
6. The semiconductor device of claim 1 , wherein the field-plate dielectric is etched below the at least one of the one or more capacitively-coupled field plates.
7. The semiconductor device of claim 1 , wherein at least one of the coupling capacitors is a capacitor network comprising two or more interconnected capacitors.
8. The semiconductor device of claim 1 , further comprising:
a non-capacitively coupled field plate electrically connected to the first ohmic contact.
9. The semiconductor device of claim 1 , wherein at least one of the coupling capacitors comprises an integrated capacitor.
10. The semiconductor device of claim 1 , wherein the field-plate dielectric comprises at least two layers.
11. The semiconductor device of claim 1 , wherein at least one of the coupling capacitors is an integrated Metal-Insulator-Metal (MIM) capacitor comprising a capacitor dielectric positioned in an overlapping region between a first capacitor plate and a second capacitor plate.
12. The semiconductor device of claim 11 , wherein the first capacitor plate is one of the one or more capacitively-coupled field plates.
13. The semiconductor device of claim 12 , wherein the integrated MIM capacitor further comprises a third capacitor plate positioned to partially overlap with the second capacitor plate across the capacitor dielectric, and wherein the third capacitor plate is one of the one or more capacitively-coupled field plates.
14. The semiconductor device of claim 1 , further comprising:
a gate contact disposed over a gate region positioned between the first ohmic contact and the one or more capacitively-coupled field plates, to form a semiconductor transistor device,
wherein the first ohmic contact is a source ohmic contact, and
wherein the second ohmic contact is a drain ohmic contact.
15. The semiconductor device of claim 14 , further comprising:
a gate field plate connected to the gate contact and extending laterally from the gate contact towards the second ohmic contact.
16. The semiconductor device of claim 14 , further comprising:
a gate dielectric disposed below the gate contact.
17. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a channel layer.
18. The semiconductor device of claim 17 , wherein the semiconductor substrate further comprises a barrier layer disposed over the channel layer, and wherein the barrier layer has a wider bandgap than that of the channel layer.
19. The semiconductor device of claim 17 , wherein the channel layer forms a terminal for one of the one or more coupling capacitors.