Vertical memory structure with array interconnects and method for producing the same
View Patent ↗Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.
1. A method for fabricating a memory cell component in a substrate, comprising:
depositing an etch-stop layer on a substrate;
depositing in-plane alternating layers of conductor and insulator materials over said etch-stop layer to create a vertical stack wherein the first and last layer is formed from the insulator material;
depositing a hardmask layer on the vertical stack;
etching a via having walls through the vertical stack to expose the etch-stop layer;
removing the hardmask;
depositing a first layer on the wall of the via;
depositing a second layer on the first layer;
depositing a third layer on the second layer;
depositing a fourth layer on the third layer;
depositing a top conductor on the fourth layer; and
forming one or more memory cells electrically connected to a portion of said top conductor and a portion of one of the in-plane layers of conductor material.
2. The method of claim 1 , wherein the first layer is a memory material formed from a metal oxide.
3. The method of claim 2 , wherein the metal oxide is one of AIN, TaO x , HfO x or TiO x .
4. The method of claim 1 , wherein the second, third and fourth layers form a selector device having a thickness of about 21 nm.
5. A method for fabricating a memory cell component in a substrate, comprising:
depositing an etch-stop layer on a substrate;
depositing in-plane alternating layers of conductor and insulator materials over said etch-stop layer to create a vertical stack wherein the first and last layer is formed from the insulator material;
depositing a hardmask layer on the vertical stack;
etching a via having walls through the vertical stack to expose the etch-stop layer;
removing the hardmask;
depositing a first layer on the wall of the via;
depositing a second layer on the first layer;
depositing a third layer on the second layer;
depositing a fourth layer on the third layer;
depositing a top conductor on the fourth layer; and
forming one or more memory cells electrically connected to a portion of said top conductor and a portion of one of the in-plane layers of conductor material, wherein the second, third and fourth layers form a selector device having a thickness of about 21 nm, and wherein the second layer is of TiO 2 and has a thickness of about 17 nm, the third layer is of Al 2 O 3 and has a thickness of about 2 nm, and the fourth layer is of TiO 2 and has a thickness of about 2 nm.
6. The method of claim 1 , wherein the fourth layer is a memory material formed from a metal oxide.
7. The method of claim 6 , wherein the metal oxide is one of AIN, TaO x , HfO x or TiO x or alloys thereof.
8. The method of claim 6 , wherein the first, second, and third layers form a selector device having a thickness of about 21 nm.
9. A method for fabricating a memory cell component in a substrate, comprising:
depositing an etch-stop layer on a substrate;
depositing in-plane alternating layers of conductor and insulator materials over said etch-stop layer to create a vertical stack wherein the first and last layer is formed from the insulator material;
depositing a hardmask layer on the vertical stack;
etching a via having walls through the vertical stack to expose the etch-stop layer;
removing the hardmask;
depositing a first layer on the wall of the via;
depositing a second layer on the first layer;
depositing a third layer on the second layer;
depositing a fourth layer on the third layer;
depositing a top conductor on the fourth layer; and
forming one or more memory cells electrically connected to a portion of said top conductor and a portion of one of the in-plane layers of conductor material, wherein the fourth layer is a memory material formed from a metal oxide, wherein the first, second, and third layers form a selector device having a thickness of about 21 nm, and wherein the third layer is of TiO 2 and has a thickness of about 17 nm, the second layer is of AIN and has a thickness of about 2 nm, and the first layer is of TiO 2 and has a thickness of about 2 nm.