Apparatuses and methods including anti-fuses and for reading and programming of same
View Patent ↗Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.
1. An apparatus comprising:
an anti-fuse bank comprising a plurality of anti-fuse elements, wherein an anti-fuse element comprises first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistor wherein length of a gate of the second transistor is different than a length of a gate of the first transistor;
a detection circuit coupled to the anti-fuse bank and comprising a plurality of current detection circuits, wherein, during a read operation, a current detection circuit of the plurality of current detection circuits is configured to provide a detection signal having a value based on a punch-through current through the anti-fuse bank; and
a latch circuit coupled to the detection circuit and comprising a plurality of latches, wherein, during the read operation, the latch circuit is configured to provide a latch signal indicative of a state of the anti-fuse element based on a value of the detection signal.
2. The apparatus of claim 1 , wherein during the read operation, the latch circuit is configured to compare the detection signal with a reference detection signal to provide the latch signal.
3. The apparatus of claim 2 , further comprising a reference current detection circuit configured to provide the reference detection signal based on a reference current.
4. An apparatus comprising:
an anti-fuse bank comprising a plurality of anti-fuse elements, wherein an anti-fuse element comprises first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistor wherein length of a gate of the second transistor is different than a length of a gate of the first transistor;
a detection circuit coupled to the anti-fuse bank and comprising a plurality of current detection circuits, wherein, during a read operation, a current detection circuit of the plurality of current detection circuits is configured to provide a detection signal having a value based on a punch-through current through the anti-fuse bank, wherein the current detection circuit comprises:
a constant voltage circuit configured to drive a constant voltage on a data line coupled to the anti-fuse element, wherein the punch-through current flows along the data line; and
a differential amplifier coupled to the data line and is configured to provide the detection signal based on the punch-through current flowing along the data line; and
a latch circuit coupled to the detection circuit and comprising a plurality of latches, wherein, during the read operation, the latch circuit is configured to provide a latch signal indicative of a state of the anti-fuse element based on a value of the detection signal.
5. The apparatus of claim 1 , further comprising:
a column selector configured to provide a first voltage to a gate of the first transistor and a second voltage to a gate of the third transistor during the read operation;
a first row selector configured to provide a third voltage to the first node during the read operation;
a second row selector configured to provide a fourth voltage to the second node during the read operation; and
an anti-fuse gate selector configured to provide a fifth voltage to a gate of the second transistor during the read operation.
6. The apparatus of claim 5 , wherein the fourth and fifth voltages are equal and the first and third voltages are equal.
7. The apparatus of claim 5 , wherein, during a program operation:
the column selector configured to provide the fourth voltage to a gate of the first transistor and to a gate of the third transistor;
the first row selector configured to provide the second voltage to the first node;
the second row selector configured to provide the second voltage to the second node; and
the anti-fuse gate selector configured to provide a sixth voltage to the gate of the second transistor.
8. The apparatus of claim 7 , wherein the sixth voltage is greater than the first, second, third, fourth, and fifth voltages.