IP Library Granted Patent US 10,198,195
Granted Patent B1
US 10,198,195 · App. 15/669,290 · Granted Feb 5, 2019

Wear leveling

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,198,195
App. No.
15/669,290
Granted
Feb 5, 2019
Kind
B1
Abstract

In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.

Claims (15)

1. A method of operating an apparatus, comprising:

selecting a portion of a memory array to be wear leveled based on how often the portion is or is to be accessed; and

wear leveling the portion;

wherein selecting the portion to be wear leveled comprises a host setting a first register that corresponds to the portion to allow the portion to be wear leveled and setting a number of second registers that correspond to remaining portions of the memory array to not allow the remaining portions to be wear leveled.

2. The method of claim 1 , comprising setting the first register and setting the number of second registers in response to a command from the host.

3. The method of claim 1 , wherein setting the first register is in response to the host determining that the portion was accessed greater than or equal to a certain number of times, and wherein setting the number of second registers to not allow the remaining portions to be wear leveled is in response to the host determining that the remaining portions were accessed less than the certain number of times.

4. The method of claim 1 , wherein selecting the portion to be wear leveled comprises selecting a portion of a ferroelectric memory array to be wear leveled.

5. An apparatus, comprising:

a host; and

a memory coupled to the host and comprising an array of memory cells; wherein:

the memory is configured to select a portion of a memory array to be wear leveled based on how often the portion is or is to be accessed; and

the host is configured to set a first register of the memory that corresponds to the portion to allow the portion to be wear leveled and to set a number of second registers that correspond to remaining portions of the memory array to not allow the remaining portions to be wear leveled.

6. The apparatus of claim 5 , wherein the host is configured to send a command that causes the memory to set the first register to allow the portion to be wear leveled and to set the number of second registers to not allow the remaining portions to be wear leveled.

7. The apparatus of claim 5 , wherein the host is configured to set the first register in response to the host determining that the portion was accessed greater than or equal to a certain number of times, and wherein host is configured to set the number of second registers to not allow the remaining portions to be wear leveled in response to the host determining that the remaining portions were accessed less than the certain number of times.

8. The apparatus of claim 5 , wherein the memory array is a ferroelectric memory array.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: FACKENTHAL, RICHARD E.; MILLS, DUANE R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043203/0033 →
Cited By (1)
US 12,314,168