Apparatuses and methods for parallel writing to multiple memory device structures

1. An apparatus, comprising:

a memory device, wherein the memory device comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations;

a memory controller coupled to the array and sensing circuitry, the memory controller configured to:

use a DRAM protocol and DRAM logical and electrical interfaces to receive the resolved instructions and/or constant data from a host; and

write the resolved instructions to a plurality of locations in the array in parallel; and

a bank arbiter, wherein the bank arbiter is configured to:

address translate a received multicast command; and

send the resolved instructions and/or constant data to a bank associated with the memory controller in order to write to a plurality of locations in the bank in parallel.

2. The apparatus of claim 1 , where the memory controller is configured to:

receive resolved constant data; and

write the resolved constant data to a plurality of locations in the array in parallel.

3. The apparatus of claim 1 , wherein the bank arbiter is configured to address translate the multicast command using a series of registers associated with the bank arbiter.

4. The apparatus of claim 1 , wherein the bank arbiter is configured to receive the multicast command via a channel controller coupled to the host.

5. The apparatus of claim 1 , wherein the apparatus comprises a bank arbiter coupled to a plurality of banks in the memory device, and wherein the bank arbiter is configured to:

receive a multicast command via an augmented dynamic random access memory (DRAM) command protocol; and

wherein the augmented DRAM command protocol is received using a DRAM control bus coupled the memory device.

6. The apparatus of claim 5 , wherein the augmented DRAM command protocol indicates to the bank arbiter that writes are to be performed in a multicast manner.

7. The apparatus of claim 1 , wherein the apparatus comprises a bank arbiter coupled to a plurality of banks in the memory device and the bank arbiter comprises logic to set bank address bits and row address bits in a series of registers for a plurality of locations in the plurality of banks.

8. The apparatus of claim 7 , wherein the bank arbiter is configured to:

receive a multicast write command via a DRAM control bus coupled to the memory device;

read the series of registers; and

send the resolved instructions and/or constant data to a relevant memory controller to write in parallel to the plurality of locations.

9. The apparatus of claim 1 , wherein the resolved instructions include processor-in-memory (PIM) commands.

10. An apparatus, comprising:

a memory device, wherein the memory device comprises a plurality of banks coupled to a bank arbiter, the bank arbiter configured to:

receive a multicast command;

read registers associated with the multicast command; and

send resolved instructions and/or constant data to the selected banks of the plurality of banks, wherein each bank comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry, wherein the memory controller is configured to:

receive resolved instructions and/or constant data sent to the bank; and

write the resolved instructions and/or constant data to the bank.

11. The apparatus of claim 10 , wherein the memory controller is configured to write the resolved instructions and/or constant data to a plurality of subarrays in the selected banks of the respective plurality of banks.

12. The apparatus of claim 11 , wherein the plurality of subarrays are different among select ones of the plurality of banks.

13. The apparatus of claim 10 , wherein the apparatus comprises a plurality of memory devices coupled to the host via a channel controller, wherein the apparatus is configured to:

receive the multicast command to relevant bank arbiters, among the plurality of memory devices, from the channel controller;

receive the multicast command to relevant memory controllers, among the selected banks of the plurality of banks of the respective memory device.

14. An apparatus, comprising:

a channel controller coupled to a plurality of memory devices, the channel controller configured to send a multicast command to the plurality of memory devices; and

a bank arbiter for each memory device coupled to the channel controller, each bank arbiter coupled to a plurality of banks in the respective memory device, each bank arbiter configured to:

receive the multicast command from the channel controller;

read registers associated with the bank arbiter responsive to the received multicast command; and

send resolved instructions and/or constant data to a selected bank of the plurality of banks based on the read registers; and

wherein each bank comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry, wherein the memory controller is configured to perform a data write operation to the selected bank of the plurality of banks.

15. The apparatus of claim 14 , wherein the resolved instructions and/or constant data are address translated by the channel controller.

16. The apparatus of claim 14 , wherein the memory controller is configured to control the sensing circuitry to:

implement logical functions including AND, OR, NOT, XOR, NAND, and NOR logical functions; and

perform non-Boolean logic operations including copy, compare and erase.

17. The apparatus of claim 14 , wherein:

the array of memory cells are dynamic random access memory (DRAM) cells and the data write operation to the selected bank is to a plurality of subarrays in the selected bank;

the memory controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces for non-multicast write operations; and

the channel controller is configured to send an augmented DRAM command to the bank arbiter in the respective memory device to indicate when a multicast write operation is to be performed.

18. A method for operating a memory device to parallel write to a plurality of locations, comprising:

receiving resolved instruction and/or constant data to the memory device, wherein the memory device comprises:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry; and

receiving a multicast write command at the memory controller;

writing the resolved instructions and/or constant data to a plurality of memory devices; and

wherein writing the resolved instructions and/or constant data comprises writing resolved instructions and/or constant data associated with processing in memory (PIM) commands to the plurality of memory devices

reading a series of registers set on the memory controller to send the resolved instructions and/or constant data to a plurality of subarrays in a bank associated with the memory controller; and

performing a multicast write operation to send the resolved instructions and/or constant data to the plurality of locations in the memory device.

19. The method of claim 18 , wherein receiving the multicast write command comprises receiving an augmented dynamic random access memory (DRAM) write command at the memory controller from a channel controller.

20. An apparatus, comprising:

a memory device, wherein the memory device comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and sensing circuitry, the memory controller configured to:

receive a block of resolved instructions; and

write the resolved instructions to a plurality of locations in the array in parallel; and

a bank arbiter coupled to a plurality of banks in the memory device, and wherein the bank arbiter is configured to:

receive a multicast command via an augmented dynamic random access memory (DRAM) command protocol; and

wherein the augmented DRAM command protocol is received using a DRAM control bus coupled the memory device.

21. An apparatus, comprising:

a memory device, wherein the memory device comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and sensing circuitry, the memory controller configured to:

receive a block of resolved instructions; and

write the resolved instructions to a plurality of locations in the array in parallel; and

a bank arbiter coupled to a plurality of banks in the memory device and the bank arbiter comprises logic to set bank address bits and row address bits in a series of registers for a plurality of locations in the plurality of banks.