IP Library › Granted Patent US 10,756,079
Granted Patent B2
US 10,756,079 · App. 15/670,649 · Granted Aug 25, 2020

Methods for forming integrated circuit having guard rings

Inventors: Ming-Song Sheu (Hsinchu, TW); Jian-Hsing Lee (Hsinchu, TW); Yu-Chang Jong (Hsinchu, TW); Chun-Chien Tsai (Yongkang, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L27/0251H01L29/0619H01L29/0623H01L29/1083H01L29/66681H01L29/7817H01L29/7835H01L29/0653H01L29/0692H01L29/1045
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Quick Facts
Patent No.
US 10,756,079
App. No.
15/670,649
Granted
Aug 25, 2020
Kind
B2
Abstract

A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Claims (23)

1. A method of forming a semiconductor device, the method comprising:

implanting a first dopant to define a first guard ring, wherein the first dopant has a first conductivity type;

implanting a second dopant to define a second guard ring, wherein the second guard ring directly contacts the first guard ring, and the second dopant has a second conductivity type;

implanting a third dopant to define a first doped region, wherein the third dopant has the second conductivity type, and the first guard ring, the second guard ring and the first doped region form a bipolar junction transistor (BJT); and

forming a transistor over the substrate, wherein the first guard ring surrounds the transistor.

2. The method of claim 1 , further comprising forming an isolation structure between the first guard ring and the second guard ring.

3. The method of claim 2 , wherein a bottom surface of the isolation structure is closer to a bottom surface of the substrate than a bottom surface of the first doped region.

4. The method of claim 1 , wherein the forming of the transistor comprises forming the transistor comprising a source electrically connected to the first doped region.

5. The method of claim 1 , wherein the forming of the transistor comprises forming the transistor comprising a drain electrically connected to the first doped region.

6. The method of claim 1 , further comprising implanting a fourth dopant to define a second doped region.

7. The method of claim 6 , wherein the implanting of the fourth dopant comprises defining the second doped region separate from the first doped region.

8. The method of claim 6 , wherein the implanting of the fourth dopant comprises implanting the fourth dopant having a different conductivity type from a conductivity type of the third dopant.

9. A method of forming a semiconductor device, the method comprising:

implanting a first dopant to define a first guard ring, wherein the first dopant has a first conductivity type;

implanting a second dopant to define a second guard ring, wherein a first portion of the second guard ring directly contacts a first portion of the first guard ring, and the second dopant has a second conductivity type;

implanting a third dopant to define a first doped region, wherein the third dopant has the second conductivity type;

forming a transistor over the substrate, wherein the first guard ring surrounds the transistor; and

forming an isolation structure, wherein the isolation structure separates a second portion of the second guard ring from a second portion of the first guard ring.

10. The method of claim 9 , wherein the forming of the transistor comprises forming the transistor comprising a source electrically connected to the first doped region.

11. The method of claim 9 , wherein the forming of the transistor comprises forming the transistor comprising a drain electrically connected to the first doped region.

12. The method of claim 9 , further comprising implanting a fourth dopant to define a third guard ring, wherein the fourth dopant has the first conductivity type, and the third guard ring directly contacts the second guard ring.

13. The method of claim 9 , further comprising implanting a fourth dopant to define a second doped region.

14. The method of claim 13 , wherein the second doped region is separated from the first doped region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2017
From: SHEU, MING-SONG; LEE, JIAN-HSING; JONG, YU-CHANG; TSAI, CHUN-CHIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 043220/0672 →
Continuity (5)
Division 14312851 · Jun 24, 2014
Continuation 13689187 · Nov 29, 2012
Division 12777672 · May 11, 2010
Provisional Application 61178613 · May 15, 2009
Related Publication 20170338218A1 · Nov 23, 2017