Three-dimensional devices having reduced contact length
View Patent ↗Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
1. A method of manufacturing a semiconductor apparatus, the method comprising:
forming a memory structure including conductor material levels and dielectric material levels alternately stacked on a surface of a substrate in a memory array region, each of the conductor material levels being separated from an adjacent one of the conductor material levels by one of the dielectric material levels;
epitaxially forming a peripheral structure over a peripheral portion of the substrate for peripheral circuits adjacent to the memory structure, the peripheral structure including silicon, the peripheral structure forming a continuous interface with the substrate, the peripheral structure having an upper surface elevated above the substrate surface, the peripheral structure including circuit components formed at least in part within the peripheral structure, wherein a bottom of the circuit components are spaced above a top surface of the substrate; and
forming contacts and interconnects coupling one or more circuit components of the peripheral circuits to the memory structure.
2. The method of claim 1 , wherein the interconnects extend between respective contacts extending to the peripheral circuits and respective contacts extending to the memory structure.
3. The method of claim 2 , wherein at least some the contacts extending to the peripheral circuits are shorter than the contacts extending to the memory structure.
4. The method of claim 1 , further comprising forming the peripheral structure after forming the multiple conductor and dielectric levels of the memory structure.
5. The method of claim 1 , further comprising depositing one or more conductive materials to form the elevated peripheral structure.
6. The method of claim 1 , wherein the upper surface of the peripheral structure is substantially coplanar with an upper surface of the memory structure.
7. The method of claim 1 , wherein the upper surface of the peripheral structure is within +50 percent of an overall height of the memory structure.
8. The method of claim 1 , wherein the upper surface of the peripheral structure is within +10 percent of an overall height of the memory structure.
9. The method of claim 1 , wherein forming the elevated peripheral structure comprises:
forming a dielectric material; and
forming a semiconductor material over exposed portions of the dielectric material.
10. The method of claim 1 , further comprising:
forming contacts from the memory structure and contacts from the peripheral structure; and
forming interconnects between the contacts from the memory structure and the contacts from the peripheral structure.
11. The method of claim 1 , further comprising forming interconnects from edges of one or more of the alternately stacked conductor material levels to devices formed on the peripheral structure.
12. The method of claim 1 , further comprising electrically coupling the peripheral structure to the substrate.
13. A method, comprising:
forming a memory array including multiple levels of memory cells, the memory array including alternately stacking conductor material levels and dielectric material levels, each of the conductor material levels being separated from an adjacent one of the conductor material levels by one of the dielectric material levels, the levels being stepped such that an uppermost surface of at least one end of a lower level of each of the conductor material levels extends beyond an overlying one of the conductor material levels and the dielectric material levels;
epitaxially forming an elevated portion adjacent to the memory array, the elevated portion formed over a peripheral portion of the surface of a substrate, the elevated portion forming a continuous interface with the substrate, the elevated portion comprising one or more regions of semiconductor material; and
forming peripheral circuitry for the memory array, including forming devices for interfacing with the memory structure on or in a surface of the elevated portion, wherein a bottom of the devices for interfacing with the memory structure are spaced above a top surface of the substrate.
14. The method of claim 13 , further comprising:
forming contacts from the uppermost surface of the memory structure that are extended beyond overlying levels;
forming contacts from one or more of the devices formed on or in the peripheral structure; and
forming interconnects between the contacts from the memory structure and the contacts from the peripheral structure.
15. The method of claim 13 , further comprising forming interconnects from edges of one or more of the alternately stacked material levels, which are more proximate the substrate, to devices formed on the peripheral structure.
16. The method of claim 13 , wherein the elevated portion includes a dielectric layer between the surface of the substrate and the elevated portion.