Receiver with clock recovery circuit and adaptive sample and equalizer timing
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
1. An integrated circuit comprising:
a data input port to receive data symbols, including a current data symbol and a subsequent data symbol, each data symbol including precursor intersymbol interference (ISI) and postcursor ISI;
an equalizer to equalize the data symbols;
a data sampler coupled to the equalizer to sample the equalized data symbols and issue the sampled data symbols as data samples;
control circuitry coupled to the equalizer, the control circuitry to issue, responsive to the data samples, measures of the precursor ISI imparted on the current data symbol by the subsequent data symbol;
the equalizer to equalize the data symbols responsive to the measures of the precursor ISI; and
an edge sampler coupled to the data input port to sample edges between the data symbols and issue the sampled edges as edge samples, the edge samples affecting timing of the equalized data symbols by the data sampler.
2. The integrated circuit of claim 1 , the control circuitry to issue measures of postcursor ISI responsive to the data samples.
3. The integrated circuit of claim 1 , further comprising phase adjustment circuitry to adjust sample timing of the data sampler responsive to the measures of the precursor ISI.
4. The integrated circuit of claim 1 , the equalizer to equalize the data symbols responsive to the data samples.
5. The integrated circuit of claim 1 , further comprising clock recovery circuitry to derive a clock signal, the data sampler to sample the data symbols responsive to the clock signal.
6. The integrated circuit of claim 1 , the control circuitry including a data filter to enable measurement of the precursor ISI responsive to a pattern of the data samples.
7. A method comprising:
receiving an analog input signal expressing a series of data symbols, including a current data symbol and a subsequent data symbol, each data symbol including precursor intersymbol interference (ISI) and postcursor ISI;
sampling the series of data symbols to recover a series of data samples;
detecting a pattern in the series of data symbols;
deriving, for the detected pattern and responsive to the series of data samples, a measure of the precursor ISI imparted on the current data symbol by the subsequent data symbol;
equalizing the analog input signal responsive to the data samples and the measure of the precursor ISI;
deriving a timing reference signal from the series of data symbols;
sampling the series of data symbols responsive to the timing reference signal; and
phase adjusting the timing reference signal responsive to the measure of the precursor ISI;
wherein deriving the timing reference signal from the series of data symbols comprises sampling edges of the series of data symbols.
8. The method of claim 7 , wherein the precursor ISI is unequalized ISI.
9. The method of claim 7 , further comprising adjusting the equalizing responsive to the measure of the precursor ISI.
10. A receiver comprising:
a data input port to receive data symbols, including a current data symbol and a subsequent data symbol, each data symbol including precursor intersymbol interference (ISI) and postcursor ISI;
a decision-feedback equalizer coupled to the date input port to equalize the data symbols;
a data sampler coupled to the decision-feedback equalizer to sample the equalized data symbols and issue the sampled data symbols as data samples;
an edge sampler coupled to the data input port to sample edges of the data symbols and issue the sampled edges as edge samples; and
control means, coupled to the data sampler and the edge sampler, for issuing a measure of the precursor ISI imparted on the current data symbol by the subsequent data symbol responsive to the data samples and the edge samples.
11. The receiver of claim 10 , the control means including a data filter to enable measurement of the precursor ISI responsive to a pattern of the data samples.
12. The receiver of claim 10 , wherein the data sampler samples the data symbols responsive to a timing reference signal, the receiver further comprising timing calibration circuitry to phase adjust the timing reference signal responsive to the measure of the precursor ISI.
13. The receiver of claim 10 , the control means further comprising clock recovery circuitry to derive a clock signal from the edge samples.
14. The integrated circuit of claim 1 , further comprising clock-recovery circuitry to generate a phase control signal responsive to the edge samples.
15. The integrated circuit of claim 14 , wherein the equalized data symbols are timed to a data clock signal and the edge samples affect timing of the data clock signal, the phase control signal affecting the timing of the data clock signal.
16. The integrated circuit of claim 15 , further comprising phase adjust circuitry to phase adjust the data clock signal responsive to the phase control signal.
17. The integrated circuit of claim 16 , wherein the phase adjust circuitry to phase adjust the data clock signal responsive to the measures of the precursor ISI.
18. The integrated circuit of claim 1 , wherein the sampling of the equalized data symbols includes sampling the equalized data symbols timed to a data clock signal, wherein affecting timing of the sampling of the equalized data symbols includes affecting timing of the data clock signal.